FPGA (Artix-7) Advice: Timing and constraints

Hi Everyone,

I'm fairly new to FPGA programming and this is my first post on the forum. I'm currently building a new camera using an Artix-7 FPGA and the Vivado design suite (using verilog). The image sensor supplies its data via 8 LVDS DDR lines and 1 LVDS clock. So far, the project is going well. I've managed to get an image off the sensor and view it properly on my PC. However, there are a few changes I need to make in order to finish the design and unfortunately I'm running into some problems. The main one is that everytime I make change (however small) the timing of the data becomes invalid. In order to solve the timing issue in the first place, I used an IDELAYE2 on each channel coming in and then adjusted the IDELAY_VALUE until it worked (Not the best way, I know, but it got it working). I have also read through this document:

https://www.xilinx.com/support/documentation/application_notes/xapp855.pdf

Which suggests you can calculate the timing delay dynamically (which would be our preferred options), but doesn't seem to give you any code to show you how to do it. I've searched around but am unable to find a good resource for this.

Another suggestion I have been given is to add constraints into the design (which will help fix the design and avoid the timing issues). When we've tried this, the build time goes from 2-3 mins to 20+ mins making it very inconvenient. Perhaps this is a sign we are doing something wrong? The build time issue occurs even if I add just the following line:

create_clock -period 3.367 -name lvdsClkP [get_ports lvdsClkP]

So I Guess what I asking is the following:

1) What's the best way to dynamically adjust the IDELAYE2?
2) How can I constrain my design without increasing the build time?
3) Are there any good resources I can be pointed to in order to help with these issues.

Any help would be greatly appreciated. I'm happy to give more details if (when) necessary.

Chris.

1) What's the best way to dynamically adjust the IDELAYE2?

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I can only give you clues from my experience in a related signalling environment...
If possible avoid using the IDELAY2 primitive. I was working with DDR RGMII signals and was trying to use the gmii2rgmii Xilinx IP which used IDELAY and ODELAY modules. I completely removed these *DELAY modules and instead modified the timing constraint file by properly utilizing the commands set_output_delay and set_input_delay for both rising and falling edge of the clocks. I found it more flexible to control this way. Another advantage of this approach is that you don't need to have the 200MHz clk necessary for these delay elements to work.
I have successfully impl this design on the AC701 board.

2) How can I constrain my design without increasing the build time?

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This is difficult to say as the build time will depend on a lot of factors.

chrgol said:

Another suggestion I have been given is to add constraints into the design (which will help fix the design and avoid the timing issues). When we've tried this, the build time goes from 2-3 mins to 20+ mins making it very inconvenient. Perhaps this is a sign we are doing something wrong? The build time issue occurs even if I add just the following line:

Click to expand...

20 minutes isn't that long of a build time. And if that is inconvenient then you likely have a very bad development process in place. I typically have on average <1 build a day when starting integration of a new FPGA design. Most of my checkout of the design functionality was done in simulation with a good testbench. Once it's built I'm only verifying that the functionality is the same and any extra builds are to either fix integration problems or add an ILA (chipscope) to determine the root cause of an integration issue. So at most I'll have maybe 2 builds in one day. Given your need to have 2-3 minute builds seems like you are simulating (interactive debugging) your design on hardware.

The whole adjusting the IDELAYs to fix I/O problems is inherently due to the lack of proper timing constraints. I can just imagine you probably have more issues than just adding a create_clock constraint to your constraints file.

"The build time issue occurs even if I add just the following line:
create_clock -period 3.367 -name lvdsClkP [get_ports lvdsClkP]"

so what exactly are you building when you don't add this line?