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how to reduce congestion in a particular clb

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UltraGreen

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how to reduce conjestion in a perticular clb

Is there a way to reduce congestion in a perticular CLB. If I have a report that says the top ten most congested CLBs are CLE_M_X74Y125 and CLEL_RX74Y125 ?

what can I do with this information to reduce congestion in the design ?
 

Re: how to reduce conjestion in a perticular clb

what can I do with this information to reduce congestion in the design ?
Click to expand...
If your design meets timing constrains - why would you bother with congestion reduction of a specific CLB ?
 

Re: how to reduce conjestion in a perticular clb

sorry for the delayed response. My design is failing in routing. there are more than 25000 nodes overlapped and in vertical congestion matrix there is more than 100% utilization. so how can I reduce this congestion ?
 

Re: how to reduce conjestion in a perticular clb

Perhaps doing some subtle changes in the RTL will solve the problem.
I'd take a second look at the architecture of the design.

What device are you using?
What does the compilation report say about LE usage (%) ?
 

Re: how to reduce conjestion in a perticular clb

I would try to understand what RTL block or what coding style is forcing the use of these specific CLBs. This might be tough to debug and might lead nowhere, i.e, just shift the congestion to somewhere else.
 

Re: how to reduce conjestion in a perticular clb

I haven't used them but given your nomenclature of "vertical congestion matrix" are you by chance using an Ultrascale part? Because it sure sounds like something that would show up for the stacked interconnect connections. If so you need to partition the design properly between stacks and not run so many signals between the stacked die.
 
Re: how to reduce conjestion in a perticular clb

yes I am using virtex ultrascale. as you mentioned the tool is spreading many blocks in multiple stacked silicon. But when I try to partition the design, specifying the pblock for critical blocks, the congestion on other modules increases. also because of all these congestion the routing time has increased to 14 hours.

The Lut utilization is 86 % and as the rtl is meant for Asic and its a complex architecture it has lot of asynchronous parts and loops which unfortunately I cannot change.

Thanks
 

Re: how to reduce conjestion in a perticular clb

Sounds like the right time to contact your local FAE for ideas...
 

Re: how to reduce conjestion in a perticular clb

UltraGreen said:
yes I am using virtex ultrascale. as you mentioned the tool is spreading many blocks in multiple stacked silicon. But when I try to partition the design, specifying the pblock for critical blocks, the congestion on other modules increases. also because of all these congestion the routing time has increased to 14 hours.

The Lut utilization is 86 % and as the rtl is meant for Asic and its a complex architecture it has lot of asynchronous parts and loops which unfortunately I cannot change.

Thanks
Click to expand...

For a design that is 86% full just partitioning the critical blocks is not going to work. You have to partition the ENTIRE design. Balance the stack crossings to the minimum set of signals and balance the amount of logic in each portion of the stacked die, e.g. two die then split the logic as close to 43%-43% and minimize the signals crossing between the die.

Realistically 86% is probably too high a utilization for an ASIC emulation design. I would probably stay below 60% if doing something like this.
 

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