hobbyiclearner
Full Member level 2
Hi,
What is RTL signoff. Where is this step(s) done in FPGA/ASIC design flow - after synthesis and before place and route or elsewhere? Is there any free tool available for the same?
Thanks,
Hobbyiclearner.
What is RTL signoff. Where is this step(s) done in FPGA/ASIC design flow - after synthesis and before place and route or elsewhere? Is there any free tool available for the same?
Thanks,
Hobbyiclearner.