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DP838 PHY transceiver and crc problem!!

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STU_KNTU

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Hi every one.
I'm supposed to transmit data with spartan 6 via Ethernet 100M.
for this reason i am using dp838 PHY .
FPGA is playing mac layer and phy will handled physical layer.
would you tell me how i can provide an optimum CRC for my data packet?
best regards
 

would you tell me how i can provide an optimum CRC for my data packet?
Click to expand...

A MAC is responsible for the Ethernet framing protocols and error detection of these frames.
CRC/FCS, DA, SA, Len/Type, etc is provided from the higher layers.
So either implement higher layers or else you have to write your own RTL for data, FCS/CRC.
 
A MAC is responsible for the Ethernet framing protocols and error detection of these frames.
Click to expand...
yes i know.
my question is what is the best way for implementing FCS/CRC in vhdl ?
 

Just implement the CRC computation in RTL. I think they are typically done using the XOR function and maybe you need to put the entire computation inside a loop. I would just write a RTL implementing Structural VHDL logic.
 
hi all .
I'm trying to generate crc code from sting of data.
for that reason i generated this hard ware based xilinx app note and this site :
**broken link removed**

Capture.JPG
but when i test this HDL design with this ethernet frame i get different result :bang:
this is ethernet frame from fpga4fun :
https://www.fpga4fun.com/10BASE-T2.html
55 55 55 55 55 55 55 D5 00 10 A4 7B EA 80 00 12 34 56 78 90 08 00 45 00 00 2E B3 FE 00 00 80 11 05 40 C0 A8 00 2C C0 A8 00 04 04 00 04 00 00 1A 2D E8 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 B3 31 88 1B
" B3 31 88 1B " => this is true crc code.
but i get this :"42 76 f0 4e"
i just shift data string in LFSR.
where is wrong??
 

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