USB Blaster download cable design

altera bitblaster protocol

I've received some mails from others who used my logic with varying success. Following are some general tips.

The ZIP on my site doesn't yet contain the updates that make AS mode work. Please manually integrate the code from my previous postings here (until I find time to make a new "release").

If it works "partially" for you, "sometimes" or "it programs the device, but the device doesn't work afterwards", your setup maybe isn't suitable for clear transmission of signals at several MHz. It may still be a critical timing in the logic, but I'm using it even slightly "overclocked" at 25 MHz and haven't had any errors since months. So I doubt it's the logic.

Try reducing the clock to the CPLD from 24 MHz to, say, 6 MHz.

Whenever I experienced problems, it was due to wrong connections, bad pullup/pulldown resistors on the target JTAG interface, or mismatch between logic levels (3.3/5 V) of Blaster vs. target JTAG interface.

For example, we once had (with a Cyclone device) 10 kOhm pullups on TDI and TMS and 10 kOhm pulldown on TCK, and experienced some problems, but they were solved after we learned that TCK pulldown should be 1 kOhm.

For the CPLD variant I actually used a EPM7064SLC44-10, because I needed 5V logic interface. If you want to attach your cable directly to a device with 3.3V logic you should another CPLD, or, as Altera does it, a level translator/driver between the devices.

The cable between CPLD to target should not exceed 10 cm in length.

Kolja

altera ftdibus.sys download

Great Job

ft2232c channel a openocd

HI,KAWK
I tested it with AS mode of ALTERA'S EP1C3, when used 24M CLK, sometimes download is failed, 6M CLK is OK for every time.
By the way, do you have any idea to transplant it to support xilinx's?

xilinx usb blaster

Hi smileyang,

regarding the failure at 24 MHz, see my earlier post. Do you have everything wired correctly? nCE, nCS, ... maybe pullups/downs are required/missing/...

Regarding Xilinx, I'm not planning any Xilinx support. Are you looking for an adapter that exactly behaves like a Xilinx Platform Cable USB, or just a possibility to program Xilinx devices with my adapter?

There's a site **broken link removed** describing a FX2 solution for Xilinx; it should be possible to adapt the FX2 firmware of my adapter for that device. Then you could change between support for Xilinx or Altera by just re-enumerating the adapter (swapping the firmware) without unplugging.

Added after some minutes:

:idea: In other words, the usb_jtag firmware (with slight modifications) could be downloaded to a Xilinx Platform Cable USB and effectively make it an Altera USB-Blaster (until next powerdown), compatible with Altera tools like Quartus!

Well, maybe there's still a little problem with the CPLD in the Xilinx cable. Either it would have to be reprogrammed each time you swap the firmware, or we need to find out what's inside (at least for simple bit banging). But as we know, it's not impossible...

Unfortunately, there's absolutely no Xilinx cable anywhere near me now, so I can't try. Anyone reading here who has a spare Xilinx Platform Cable USB, willing to donate it for this development? X-Mas time...

Kolja

ftdi+usb-blaster clone

I can write to an EPCS16 using Active Serial Mode, and reading and verification works as well!
But failed to write an EPCS64 using Active Serial Mode.

expected jtag id code alera quartus programmer

Did you try the EPCS64 in the same circuit/board/setup as the EPCS16, or in a different environment? Do you have another programming adapter (e.g. Altera USB-Blaster or Byteblaster) to verify the correct operation of the EPCS64 in your setup?

byteblaster tck pulldown

This EPCS64 in another board,I can write to it successfully using ByteblasterII.
I found the output (DCLK/TCK) exceed 25Mhz when using Active Serial Mode.
The input clock of EPM7064 is 24Mhz.

vid_09fb&pid_6001 driver download

Hi kawk,
you did a good job indeed!

can you make a new "release" for USB BLASTER on your website.

usb blaster schematic diagram pdf max

zhongyb, I'll make a release soon and announce it here. But it won't contain many enhancements beside the AS mode and better encoded state machine.

infostar, how did you measure the CLK freq? 25 MHz from a device clocked at 24 MHz sounds somewhat strange. Does it work with a slower clock?

Some more general info:

I was working on the proposed variant for cheap SiLabs F326. It turned out to be incompatible because F326 only has EP1, no EP2. Might work on F320/F321. I then tried to find out if it is possible to load custom firmware on the SiLabs Toolstick BA. That could become a cheap alternative (ca. USD20 + USD10 for the JTAG connector - not full featured though). It is possible in principle, but at this time simply too time consuming to implement.

Furthermore I'm making progress with evaluation whether it is possible to load customized firmware on a Xilinx Platform Cable USB (see prior posting). I now own a Xilinx Spartan 3E Starter Kit (with embedded USB "cable") and already learned quite a lot about the FX2/CPLD relationship.

Kolja

altera usb cable detect problem

kawk,
Thank you very much for your timely response and kindness!
But, where can I find the schematics of your "USB JTAG Adapt"?Does this code apply to the "ALTERA USB BLASTER" similarly?
Thank you again and again!

vid_09fb&pid_6001 driver

Hi,

does this code apply to the "Altera USB BLASTER" similarly?

Click to expand...

In principle, you could re-program an USB Blaster CPLD with my VHDL code (after you defined the correct IO pin assignments) and the device would still appear to be an USB Blaster and could be used as before with Quartus etc.
But it's not exactly the same. I don't know the exact contents of the CPLD in the Blaster. Probably some situations exist in which the Altera device performs better than mine.

I don't have detailed schematics. For my tests I just wired a FTDI module with FT245RL directly to an EPM7064 with a few external resistors and pinheader for the JTAG connection, exactly as documented in their respective datasheets.

Kolja

urjtag cable usb

Hi,

I just uploaded a new release at http://www.ixo.de/info/usb_jtag/ including all the drivers (OpenOCD and openwince), many readme files, updated CPLD code with AS mode and FX2 code now properly using my USB VID/PID.

Please let me know if you find any errors, even typos in the readme files! Thanks for your help in advance.

Kolja

terasic usb blaster+driver

Look at https://sourceforge.net/projects/xilprg cblsrv-01 - Xilinx CableServer compatible with USB blaster.

usb clone altera

hi,kawk:there are some error in my usb blaster,first,the device is not stable,sometimes,the usb blaster can find the target device,but sometimes,the usb blaster can not find the target device,and this time,the quartus tell me that the jtag server can not find the programing device,so,I plug out the usb blaster,and plug the usb blaster into the USB port,then,the usb blaster can find the target device
secondly,I use EPM7064STC44-10 as the usb blaster logic device,but the usb blaster can not find the target device of EPM7064STC44-10,why?there is not the level tramsfer chip between the usb blaster and the target device.
lastely,the USB blaster have not the quick velocity,and I found the velocity is not fast than the byteblaster II,why?

xilinx pulldown on tck

Hi khach, from where do you have the info that xilprg/cblsrv works with USB-Blaster? A quick look at the source shows support for Digilent USB cable only - probably not compatible?!

Hi lyxer, the readme.txt files in the ZIP contain some hints regarding stability. Did you use CPLD source from old or current release ZIP? I do not understand your second question.

Regarding speed, usb_jtag isn't necessarily faster than a ByteBlaster. For day-to-day debugging (lots of small transfers) it's probably even slower due to the latency for USB transfers. And since usb_jtag and USB-Blaster are not the same, their speed also may differ; an USB-Blaster is probably faster. Speed wasn't my primary goal when developing the adapter.

Kolja

altera usb blaster schematic

Hi,

I've restructured the FX2 firmware code; it's now based on USRP from GNU Radio Project.

* Use SDCC instead of Keil compiler
* Hardware adaption is now easier
* Emulated EEPROM content is computed on-the-fly from descriptor data

It can be used on Xilinx Spartan-3E Kit and probably Xilinx Platform Cable USB (XPCU) with original CPLD (at least CPLD version 18), instead of Xilinx firmware . On the XPCU, it can access the internal chain (CPLD) or the external chain (X3S500, PROM and CPLD on Starter Kit).

In other words, the new firmware can convert a XPCU to an usb_jtag cable for a while (volatile!), making it compatible with all the host software that can access my usb_jtag.

Kolja

altera usbblaster replacement

And how do you load the firmware under Windows?

Under Linux the fxload program is used...but is there some tool available from Cypress?


cheers
davorin

altera usb blaster ftd2xx

From Cypress there is a tool to upload firmware, but it works only as long as the Cypress driver is used for the currently enumerated device. An alternative is "fxpush", based on libusb-win32:

http://www.ixo.de/info/usb_jtag/fxpush.c

Kolja

lattice usb cable

Hi kawk
I have tested your design (FT245 + CPLD ) with a hand made board and got successul results except below.
When there is not any good JTAG connection (i.e disconnected or other conditions) between target board and your USB- BLASTER, The detection and error reporting of Quartus II is too long compared with commercial USB-BLASTER made by ALTERA. You can try it and may be get same result. Could you modify this ?

Thanks and Best Regards,
Bcarson

byteblaster usb epm7064

Hi,

Could you please describe the differences in more detail?!
What do you mean by "disconnected" - the adapter itself or the target?
How long does it take with the one or the other adapter?
Why do you think it is "too" long?
Are you using the CPLD or the FX2 variant?
If you're using the CPLD variant, what clock are you using?

If you're using the CPLD variant, there are some intermediate states in the state machine that make it (maybe) slower than an USB Blaster. You could try to omit them, but then you'll have to give an explicit reset signal to the state machine at powerup. I won't do that because I'm happy with the logic as is, and speed is sufficient for me.

Kolja