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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 --RFID TOP-LEVEL DESIGN library IEEE; use IEEE.std_logic_1164.all; ENTITY RFID IS --I/O PINS PORT ( CLK, RESET,R_X : IN STD_LOGIC; A_o: out std_logic_vector (4 downto 0); FLAG_o: OUT STD_LOGIC ); END ENTITY; ARCHITECTURE CKT OF RFID IS --COMPARE COMPONENT COMPONENT compare is generic(W: integer := 8); port( clk, reset: in std_logic; clr_flag, set_flag: in std_logic; din: in std_logic_vector(w-1 downto 0); a: out std_logic_vector (4 downto 0); flag: out std_logic ); END COMPONENT; --BAUD RATE GENERATOR COMPONENT COMPONENT mod_326 is generic( N: integer := 9; M: integer := 326 ); port( clk, reset: in std_logic; max_tick: out std_logic; q: out std_logic_vector(N-1 downto 0) ); end COMPONENT; --SERIAL RECIEVER COMPONENT COMPONENT UART_1 is generic( DBIT: integer := 8; SB_TICK: integer := 16 ); port( clk, reset: in std_logic; rx: in std_logic; s_tick: in std_logic; rx_done_tick: out std_logic; dout: out std_logic_vector(7 downto 0) ); end COMPONENT; --signals signal rx_d: std_LOGIC; signal dout_m:std_logic_vector(7 downto 0); signal s_tick_m:std_LOGIC; signal q_out: std_logic_vector(8 downto 0); BEGIN gene: mod_326 port map (clk,reset,s_tick_m,q_out); UART_2: UART_1 port map (clk,reset,R_x,s_tick_m ,rx_d,dout_m); comp_1: compare port map (clk,reset,'0',rx_d,dout_m,A_o,flag_o); end ckt;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity UART_1 is generic( DBIT: integer := 8; SB_TICK: integer := 16 ); port( clk, reset: in std_logic; rx: in std_logic; s_tick: in std_logic; rx_done_tick: out std_logic; dout: out std_logic_vector(7 downto 0) ); end UART_1; architecture arch of UART_1 is type state_type is (idle, start, data, stop); signal state_reg, state_next: state_type; signal s_reg, s_next: unsigned(3 downto 0); signal n_reg, n_next: unsigned(2 downto 0); signal b_reg, b_next: std_logic_vector(7 downto 0); begin process(clk, reset) -- FSMD state and data regs. begin if (reset = '1') then state_reg <= idle; s_reg <= (others => '0'); n_reg <= (others => '0'); b_reg <= (others => '0'); elsif (clk'event and clk='1') then state_reg <= state_next; s_reg <= s_next; n_reg <= n_next; b_reg <= b_next; end if; end process; -- next state logic process (state_reg, s_reg, n_reg, b_reg, s_tick, rx) begin state_next <= state_reg; s_next <= s_reg; n_next <= n_reg; b_next <= b_reg; rx_done_tick <= '0'; case state_reg is when idle => if (rx = '0') then state_next <= start; s_next <= (others => '0'); end if; when start => if (s_tick = '1') then if (s_reg = 7) then state_next <= data; s_next <= (others => '0'); n_next <= (others => '0'); else s_next <= s_reg + 1; end if; end if; when data => if (s_tick = '1') then if (s_reg = 15) then s_next <= (others => '0'); b_next <= rx & b_reg(7 downto 1); if (n_reg = (DBIT - 1)) then state_next <= stop; else n_next <= n_reg + 1; end if; else s_next <= s_reg + 1; end if; end if; when stop => if (s_tick = '1') then if (s_reg = (SB_TICK-1)) then state_next <= idle; rx_done_tick <= '1'; else s_next <= s_reg + 1; end if; end if; end case; end process; dout <= b_reg; end arch;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 library ieee; use ieee.std_logic_1164.all; entity compare is generic(W: integer := 8); port( clk, reset: in std_logic; clr_flag, set_flag: in std_logic; din: in std_logic_vector(w-1 downto 0); a: out std_logic_vector (4 downto 0):="00000" ; flag: out std_logic ); end entity; architecture arch of compare is signal dout: std_logic_vector(39 downto 0); signal buf_reg, buf_next: std_logic_vector(W-1 downto 0); signal flag_reg, flag_next: std_logic; begin process(clk, reset) begin if (reset = '1') then buf_reg <= (others =>'0'); flag_reg <= '0'; elsif (clk'event and clk='1') then buf_reg <= buf_next; flag_reg <= flag_next; end if; end process; process (buf_reg, flag_reg, set_flag, clr_flag, din) variable count: integer:=0; begin buf_next <= buf_reg; flag_next <= flag_reg; if (set_flag = '1') then buf_next <= din; flag_next <= '1'; elsif (clr_flag = '1') then flag_next <= '0'; end if; case count is when 0 => dout(39 downto 32)<= buf_reg; count := count + 1; when 1 => dout(31 downto 24)<= buf_reg; count := count + 1; when 2=> dout(23 downto 16)<= buf_reg; count := count + 1; when 3 => dout(15 downto 8)<= buf_reg; count := count + 1; when 4 => dout(7 downto 0)<= buf_reg; IF dout="0000000001111110100010101110011100010011" then a<="00111"; else a<="00000"; end if; count := 0; when others => count := 0; end case; end process; -- output logic flag <= flag_reg; end arch;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity mod_326 is generic( N: integer := 9; M: integer := 326 ); port( clk, reset: in std_logic; max_tick: out std_logic; q: out std_logic_vector(N-1 downto 0) ); end entity; architecture arch of mod_326 is signal r_reg: unsigned(N-1 downto 0); signal r_next: unsigned(N-1 downto 0); begin process(clk, reset) begin if (reset = '1') then r_reg <= (others => '0'); elsif (clk'event and clk='1') then r_reg <= r_next; end if; end process; -- next state logic r_next <= (others => '0') when r_reg=(M-1) else r_reg + 1; -- output logic q <= std_logic_vector(r_reg); max_tick <= '1' when r_reg=(M-1) else '0'; end arch;