Sunayana Chakradhar
Member level 5
Hello All,
I am using Zynq 7000 SOC in my design. I have enabled UART 0 and UART1 in the PS with extra modem signals. In addition to this, I need to create 2 more UARTs on the PL side for which I have chosen UART 16550 IP core. All 4 UARTS are 4 wired. ie they include TX, RX, RTS and CTS signals. I don't need the other signals which vivado automatically gives like DCDN, Rin etc. Few signals which are of input type, I connected them to a constant 0. However the signals of the UART which are of output type cannot be connected to any constant. When implement the design and open it, the tool asks me to assign pins to these extra signals as well which is not desired in my project. How do i remove these extra redundant signals of the UART? I tried to edit the UART HDL file as well but its a read only file. Please suggest
Regards
I am using Zynq 7000 SOC in my design. I have enabled UART 0 and UART1 in the PS with extra modem signals. In addition to this, I need to create 2 more UARTs on the PL side for which I have chosen UART 16550 IP core. All 4 UARTS are 4 wired. ie they include TX, RX, RTS and CTS signals. I don't need the other signals which vivado automatically gives like DCDN, Rin etc. Few signals which are of input type, I connected them to a constant 0. However the signals of the UART which are of output type cannot be connected to any constant. When implement the design and open it, the tool asks me to assign pins to these extra signals as well which is not desired in my project. How do i remove these extra redundant signals of the UART? I tried to edit the UART HDL file as well but its a read only file. Please suggest
Regards