Random question on Verilog

abhisheknayak95 · May 30, 2016

Electronic Scoreboard : (VERILOG problem)

An Electronic scoreboard is used to display information of a game like points earned by a team, set points and winner. There are two teams in this game. Rules of the game are as follows :

1. A team has to score minimum 12 points and last two consecutive points must be scored by the same team to earn a set point.
2. If last two consecutive points are not scored by the same team, team scoring 15 points first will be awarded a set point.
3. To win the match one of the teams has to earn three set points.

Whenever a team gains a point, the score boy presses a key corresponding to that particular team and rest of the decision is made by the score board circuit. Final result of the match is also displayed on the score board by turning ON a LED. Try to use optimal number of resources.

Write a VERILOG code for the above problem.

Please help me with this question. I need an answer asap !

d3javu · May 30, 2016

this looks like a homework question. I'm not going to give out the answer but will give you a hint. For this kind of scenarios, you should use Finite State Machine. I believe you have learned FSM before dive into verilog. Do study a little about it and then try to convert your problem into FSM.

vGoodtimes · May 30, 2016

you can use two 0-15 counters, two 0-3 counters, a bit for "15 reached once", and a bit for "last point player 1".

from here, it is just some if/else statements.

abhisheknayak95 · May 31, 2016

I am new to VERILOG. I want to have a look at this answer before proceeding further.
Please help me with this.
Thank you.

TrickyDicky · May 31, 2016

abhisheknayak95 said:
I am new to VERILOG. I want to have a look at this answer before proceeding further.
Please help me with this.
Thank you.

isnt the point of the assignment you come up with your own answer?

ads-ee · May 31, 2016

TrickyDicky said:
isnt the point of the assignment you come up with your own answer?

Naw, I think the new engineering education system pushes for how to get your answers from edaboard, hence the desperate pleas of need this ASAP being sent from their phone during their interview ;-)

slutarius · Jun 1, 2016

Read the tennis rule I suggest !!

TrickyDicky · Jun 1, 2016

ads-ee said:
Naw, I think the new engineering education system pushes for how to get your answers from edaboard, hence the desperate pleas of need this ASAP being sent from their phone during their interview ;-)

**broken link removed**

abhisheknayak95 · Jun 1, 2016

it's not that i haven't tried. My tutor is not available now, so I am seeking help of you guys.
If you don't want to help, then please don't!

TrickyDicky · Jun 1, 2016

abhisheknayak95 said:
it's not that i haven't tried. My tutor is not available now, so I am seeking help of you guys.
If you don't want to help, then please don't!

We want to help, but we're not here to do your work for you.
Why not ask a question that we can help with

ads-ee · Jun 1, 2016

abhisheknayak95 said:
it's not that i haven't tried. My tutor is not available now, so I am seeking help of you guys.
If you don't want to help, then please don't!

Then don't ask us to write the code for you. Write your own implementation post it and tell us what you are unable to fix. If that tutor was writing code for you they were doing you a disservice, because you won't learn how to do something on your own.

vGoodtimes · Jun 2, 2016

@abhisheknayak, can you at least post the code you have written thus far?

abhisheknayak95 · Jun 2, 2016

ads-ee said:
Then don't ask us to write the code for you. Write your own implementation post it and tell us what you are unable to fix. If that tutor was writing code for you they were doing you a disservice, because you won't learn how to do something on your own.

Code Verilog - [expand]
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module scoreboard(clk1,clk2,set1,set2,m1,m2);
input clk1,clk2;
output reg [1:0]set1,set2;
output reg m1,m2;
reg [3:0]q1,q2;
reg [2:0]p;
reg [0:1]z;
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
 
initial
begin
    p=s0;set1=0;set2=0;m1=0;m2=0;q1=0;q2=0;z=0;
end
 
always@ (posedge clk1 or posedge clk2)
begin
 
    case(p)
        s0: begin
                if(clk1)
                    p = s1;
                else
                    p = s2;
                    
                z=0;
            end
        s1: begin
                if(clk1)
                    p = s3;
                else
                    p= s2;
                    
                z=0;
            end
        s2: begin
                if(clk1)
                    p= s1;
                else
                    p = s4;
                    
                z=0;
            end
        s3: begin
                if(clk1)
                    p = s3;
                else
                    p = s2;
                
                z = 2'b10;
            end
        s4: begin
                if(clk1)
                    p = s1;
                else
                    p = s4;
                    
                z = 2'b01;
            end
    endcase
end
 
always@ (posedge clk1)
begin
    q1 = q1+1;
    if( (q1>=12 && z[0]==1) || (q1==15) )
    begin
        set1 = set1 + 1;
        q1 = 0;
    end
    if (set1 == 3)
        m1 = 1;
end
 
always@ (posedge clk2)
begin
    q2 = q2+1;
    if( (q2>=12 && z[1]==1) || (q2==15) )
    begin
        set2 = set2 + 1;
        q2 = 0;
    end
    if (set2 == 3)
        m2 = 1;
end
 
endmodule

The code is not efficient. But i am getting the output. Help me with this !

ads-ee · Jun 2, 2016

Code Verilog - [expand]
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always@ (posedge clk1 or posedge clk2)
begin
    case(p)
        s0: begin
                if(clk1)
                    ...
                else
                    ...
            end
...
    endcase
end

This is impossible to implement, there is no such thing as a two clock flip-flop, and then level sensing the clock is a poor design decision that can result in failure to close timing.

Besides this you are using blocking assignments everywhere in code that is supposed to model flip-flops, this is NOT how you model a flip-flop you should be using non-blocking assignments.

I don't think I've ever read a Verilog book or Verilog tutorial that would suggest coding in this fashion. Where did you get the idea this "works"?

- - - Updated - - -

FYI, initial blocks in Verilog are NOT synthesizable, they are ignored by synthesis tools, so if you are relying on the power up state of a FF to be at the initial block's state then it won't happen. Use/add a reset to the code or initialize the signal in the declaration (ISE, Vivado, and Quartus will all initialize the FF to the correct value or use NOT gate pushback to ensure the signals start in the correct state).

- - - Updated - - -

Code Verilog - [expand]
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always@ (posedge clk2)
begin
    q2 = q2+1;
    if( (q2>=12 && z[1]==1) || (q2==15) )
    begin
        set2 = set2 + 1;
        q2 = 0;
    end
    if (set2 == 3)
        m2 = 1;
end

The code above will also result in a simulation synthesis mismatch as the blocking assignments from the always block are also used in the always block.

As you can see in the waveform above m1 changes immediately when set1 changes to 3 and persists, this is impossible for a physical FF to emulate as the comparison for set1 == 3 has to be done on a clock edge and the clock edge where the yellow cursor is located is the clock edge that caused set1 to become 3.

The same thing is happening with q1, q2, and set2.

- - - Updated - - -

Take a look at this site with examples of synthesizable code for various typical constructs used in a design.

- - - Updated - - -

I'll give you a hint for how to architect this by giving you a drawing (no code).

The debouncing is necessary as mechanical switches will "chatter" between 0 and 1 when being engaged. You also need to edge detect the signals as they will hold state for a long period of time relative to any clock you are likely to use.

Your original concept was an asynchronous design, with the switch inputs used as "clocks". Regardless what they are teaching at your school, this is not how design digital is done in the real world.

vGoodtimes · Jun 3, 2016

First, I'd like to thank you for the consistent indentation scheme for your code. The majority of posters have random indentation which makes it hard to read.

Especially when learning, you should use descriptive names and even comment exactly what a reg means.

As mentioned, FPGAs don't use dual-clocking. Normally you would have something like:

Code:

always @ (posedge system_clock) begin

  if (point_input[0]) begin
    ...
  end

  if (point_input[1]) begin
    ...
  end
end

There are several ways to write the code if you want to avoid duplication of text. The key point here is that a system clock runs at a fixed rate, and on each cycle events either happen or they do not. Specifically, not all clock cycles will perform work.

Avoid using "=" inside of an always @ (posedge/negedge) block. There are only a few times when this is ok to do. The issue is that always blocks can be evaluated in any order according to the LRM. "=" updates a value immediately. This can lead to simulation mismatches.

notice that q1 is your counter. However you reset it once you reach 12+ or 15. Likewise both teams can score the "first to 15" goal.

you have multiple always@ (posedge clk) blocks. The blocking assignments might let this work in simulation, but in hardware you will actually be defining a "pipeline". Replace all "=" with "<=" and you'll notice what hardware will do.

is it that the "last two points" does not include the current point being scored? I'm wondering if your state machine is correct.

I probably wouldn't use a full state machine for this. You don't really need it. you just need to keep track of who scored the last two points using a shift register. Because 12 > 2, you can initialize it to 00 without any issues.

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