rahdirs
Advanced Member level 1
Why does reducing frequency allow for downsizing of transisitors (Weste & Harris)
Hi,
I've recently started reading CMOS VLSI Design by Weste & Harris. While reading, I've found this statement " Reducing frequency allows for downsizing transistors/ using a lower supply voltage, which has an even greater impact on power ".
Why does reducing frequency allow downsizing ? Is it because as you reduce frequency, you can operate with more delay & hence can reduce the width of transistors ? And as you reduce the size of transistors, you can use a lower Vdd with not much change in charging & discharging times ? Am I correct in my reasoning or is there a different reason ?
Regards,
rahdirs
Hi,
I've recently started reading CMOS VLSI Design by Weste & Harris. While reading, I've found this statement " Reducing frequency allows for downsizing transistors/ using a lower supply voltage, which has an even greater impact on power ".
Why does reducing frequency allow downsizing ? Is it because as you reduce frequency, you can operate with more delay & hence can reduce the width of transistors ? And as you reduce the size of transistors, you can use a lower Vdd with not much change in charging & discharging times ? Am I correct in my reasoning or is there a different reason ?
Regards,
rahdirs
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