Serwan Bamerni
Member level 2
Two Dimension memory
Hello everyone
As I know all memory models in FPGA are 1-Dimension array when generated either by logic ip core or manually (self programming), in which each location address is specified by a number like mem(5) that refer to position 6 in the memory model mem.
My question is, it is possible (and legal) to infer a 2-Dimension array to save some intermediate value of an image so each location address is specified for example as mem(4,5)
I know how to generate 2-Dimension array in VHDL but as I said I ask about it is possibility, synthesizability and legality to do that in building an image processing system?
Hello everyone
As I know all memory models in FPGA are 1-Dimension array when generated either by logic ip core or manually (self programming), in which each location address is specified by a number like mem(5) that refer to position 6 in the memory model mem.
My question is, it is possible (and legal) to infer a 2-Dimension array to save some intermediate value of an image so each location address is specified for example as mem(4,5)
I know how to generate 2-Dimension array in VHDL but as I said I ask about it is possibility, synthesizability and legality to do that in building an image processing system?