Deka87
Newbie level 6
Dear all,
I've a problem during the AMS simulation in virtuoso.
I have created a VHDL module, which generates a PRBS signal and I have imported its in the library manager correctly, because the AMS simulation works well.
There is a problem when i try to connect the output of the VHDL module to a electrical model (i.e. vcvs or my verilog-AMS model).
During the simulation, in the log is shown the following error:
ncelab: *E,BLPMDE (./netlist.vams,26|24): VHDL BUFFER and LINKAGE port cannot occur at mixed language mixed domain boundary.
I've tried to google, but I don't find any results.
Can you help me?
Thanks a lot
Francesco
I've a problem during the AMS simulation in virtuoso.
I have created a VHDL module, which generates a PRBS signal and I have imported its in the library manager correctly, because the AMS simulation works well.
There is a problem when i try to connect the output of the VHDL module to a electrical model (i.e. vcvs or my verilog-AMS model).
During the simulation, in the log is shown the following error:
ncelab: *E,BLPMDE (./netlist.vams,26|24): VHDL BUFFER and LINKAGE port cannot occur at mixed language mixed domain boundary.
I've tried to google, but I don't find any results.
Can you help me?
Thanks a lot
Francesco