[SOLVED] Help on seed for true random generator in VHDL

Hi all,

I am trying to use true random values to feed my testbench for functional simulation. I am using the random package from OSVVM but the sequence is pseudo random. Is it possible to use system time to generate the seed in VHDL?

I want to use the system time not simulation time, so i have different values each time i run the simulation. I could not find any VHDL example for a true random generator. Is it a bad idea to configure simulation randomly? I know i should rather aim for coverage, i am still a beginner on that topic.

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I just found the $gettime command. Trying to use this in my simulation macro file, then pass it throu a generic to my testbench. It is Aldec spezific though, and i don't know the data type it returns.

All numbers that calculated are pseudorandom. Even if you feed them with the system time, the resulting sequence is psuedorandom, based on a given distribution. Getting truly random input in a VHDL testbench would be very difficult, as it would hard to hook into a RNG system function (which usually uses something like thermal noise to create a random number.

The whole point about using a known seed in testbenches is for reproducibility. for a given seed, you get a given sequence. Hence if you find a bug, you can easily reproduce the sequence to debug and fix the bug.

I would highly suggest you stick to a given seed (or set of seeds), and just run the test for longer to get more coverage. This way, if theres a bug, you can fix it.
Is there some special reason for using OSVVM? this gives a wealth of number distributions and coverage metrics, but did you know there is a random number generator built into VHDL in the ieee.math_real package? the uniform function takes two positive seed values and gives a pseudo random real between 0 and 1. You can use this to derrive random numbers in any types. I think even part of OSVVM uses this function underneath.

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PS. I dont mean to discourage the use of the OSVVM package. It is very good, but it sounds like you arnt fully aware of testing theory and practice.

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You would only go with a "random" seed if you were running your testbench through regression runs, to try and find any final bugs. For inital debug, you want to stick with a single (or a known set) of seeds.

You may be interested in a cryptographically secure pseudo-random number generator (CSPRNG).

Why do you need to blast random values in?
Are you unsure how your program deals with unspecified inputs?
If you have others => clauses(or defaults) or don't spec them in the if statement then you should be fine.

TrickyDicky said:

The whole point about using a known seed in testbenches is for reproducibility ... to debug and fix the bug.

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Yes, i am aware of that. This is why i thought it would not be that common since i did not find an example on the net. My intention was to, like you said, use it as a companion to try and find any final bugs.

TrickyDicky said:

I think even part of OSVVM uses this function underneath.

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That is correct. The random function actually uses the uniform function from ieee.math_real.

TrickyDicky said:

Is there some special reason for using OSVVM?

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I am using OSVVM as a starting point for verification and simulation coverage. I was reading a little about testing theory and am trying to apply it, still beginning in this matter though.

I could not pass the time to my testbench through the macro file, but i think i leave that now and use only known sets of seeds.

Btw - Your task would be easier in SystemVerilog - you can easily get the system time via the $system("time") function.