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PNP vs NPN in voltage divider bias circuit

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muheeb16

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I am designing a simple bias circuitry for JFET using a PNP transistor (it is connected in voltage divider bias) because my instructor asked me to use it.I have come across NPN a lot.I don't know why he wants me to use PNP.What can be the advantages of it?
 

Can you post some schematics?
 

How's the circuit related to JFET?

The resistor values look inappropriate (transistor in saturation). What do you want to achieve?
 

The collector is connected to the gate and the emitter to the drain of JFET....Keep in mind I am using dual supply....Also why are you saying its in saturation.The collector has a negative voltage which as I told you I have connected to gate of JFET and the base has a positive voltage....So Collector base junction is reverse biased.Right?How is it in saturation.Forgive me if I am wrong....!
 
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Most of the current through 300ohm resistor goes to the drain (the outgoing line) of the JFET and very less flows from emitter to collector.the drop across R3 is very less...and hence collector voltage is negative.My project works fine...Collector voltage is indeed negative otherwise my JFET wouldn't have worked....Also can you tell me how to calculate for the region my transistor operates in.I will be very grateful.....
 

Most of the current through 300ohm resistor goes to the drain (the outgoing line) of the JFET and very less flows from emitter to collector.
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O.K. Come back with meaningful schematics.
 

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