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I'd expect that a 6-bit updown counter will take at least as much power/area as 6-bit upcounter, and possibly a bit more. I'd expect area increase to be slightly more pronounced than power increase. But as TrickyDicky said, try and find out for yourself.
If you are in an FPGA - you should not be using any sort of counters for frequncy division, unless you are generating a clock enable. Creating new clocks should be done as the output of an MMCM or PLL
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