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Relationship between XILINX logic cells to ASIC gates

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ashpigel

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Hello,
I want to know the relationship between XILINX VIRTEX II and VIRTEX 4 FPGAs logic cells (1 LUT + 1 FF) to ASIC gates, I know the formal numbers but the real numbers are different because the efficiency of each logic cell (or slice) is low.
Does someone knows to tell me the real numbers after taking the efficiency into account.
Thanks
 

Not sure abt the VIRTEX 2,4 LUT sizes.
But typically 5-8 gates in an FPGA is equivalent to one gate in std cell ASIC.

ie a 1 million gate asic logic needs a 5-8 million programmable gate FPGA to fit in.

varies with FPGA architecture and FPGA utilisation though.
 

Seems there is an app note in Xilinx's web which mentions this.

zcq
 

Rule of thumb:

No. of Logic Cell x 7 = No. of ASIC gates.

for example, XC2V6000 is 76K Logic Cell.
76x7 =~ 500K gates.

This is a very conservitive measure. Usually, the marketing from Xilinx will tell you x10
 

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