ramya15
Newbie level 6
i tried to compile a verilog code for divided by2 circuit using flip flop , its needs a feedback so i used a buffer at the output, the code got successful compilation but while loading i got this error
please anyone help me out , have any1 encountered these kind of errors
here is the code for divide by2 circuit
Code dot - [expand] 1 2 3 4 5 # Loading work.my_buf # ** Fatal: (vsim-3365) C:/altera/10.0/divdes.v(7): Too many port connections. Expected 2, found 3. # Time: 0 ns Iteration: 0 Instance: /divi1/n1 File: C:/altera/10.0/buf.v # FATAL ERROR while loading design # Error loading design
please anyone help me out , have any1 encountered these kind of errors
here is the code for divide by2 circuit
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 module divi1(q,qb,clk); output q,qb; input clk; wire x; wire y; wire a; my_nand n1(x,a,clk); my_nand n2(y,x,clk); my_nand n3(q,x,qb); my_nand n4(qb,y,q); my_buf b1(a,qb); endmodule
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