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disadvantages of inferring latches.

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inferring latch

Hi,

if a signal is not activly driven under all conditions a latch will be infered. what are the disadvantages of such latches?

thanks
 

disadvantage of using latches

Always latches in signal path is critical that they produce glitches. They are level senstive .
 

inferring latches

(1) add the complexity of static timing analysis. in this case the latch enable signal is the clock signal; if not, then only complicates the combinational path between the two registers.
(2) make the design less reusable
(3) may cause undesired results when glitches occur on the latch enable signal; however this is not very serious with detailed consideration.
 

disadvantages of latches

According to modern ASIC design guideline , there must be no any latchs in your design. Dont ask why!Except you use Latch as sequential cell.
 

disadvantage of latch

Inferring latch also makes DFT more difficult.
 

latches disadvantage

The size of Latch is only about 1/3 of FF and consume lesser power,
so use Latch only in datapath design (FIFO) .
 

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