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immediate assertion in systemverilog (SVA)

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Mina Magdy

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Hi
I would like to know
1) what is the working phases of immediate assertion?
2) does immediate assertion have any use other than asynchronous checks?
3) could i write immediate assertion inside program block as i think it will be concurrent assertion not immediate ?
4) does i have the ability to bind an immediate assertion block with immediate assertion or i must write immediate assertion inside the RTL?

thanks in advance.
 
Last edited:

Hi Mina Magdy,

I would like to answer few of the above queries related to Assertions ....
1. Immediate assertions works as the Blocking region but in Reactive region.
3. You cannot code immediate assertions in program block just like assign in module but you can make use of concurrent assertions in initial block.
4. You can use bind construct to bind the module/program block having assertion statements to the dut/rtl block which you want to add assertion checks.

Code: 
 [syntax=verilog]
     module dut (port list A);
       //<DUT BODY >
     endmodule
     program assertions(some/all of the ports from port list A);
       //<assertions/coverage body>
    endprogram
   module bindmodules();
      bind dut assertions assertions1(.*);  //which will automatically finds the dut instances and creates the instances of assertions block inside the dut module.
   endmodule
[/syntax]

Hope this help!
 
Last edited:

sivateja.m's response is totally incorrect.

1. immediate assertions execute in what ever region the procedural statements around it execute; the same as an if procedural statement would execute. There is also a deferred immediate assertion that also evaluates its expression along with the procedural statements around it, the the action block is triggered in a later region.
2. immediate assertions are useful where this is no recognizable synchronous clock, like a latch or combinatorial logic, as well as unsynthesizable code like inside your testbench.
3. It does not matter if you use immediate assertions in a program block or module, the semantics are the same as any procedural code. I do not recommend anyone using program blocks in SystemVerilog. See https://go.mentor.com/programblocks
4. You cannot use a bind statement to insert an immediate assertion into an existing block of procedural RTL code. You can use bind to insert module that contains an immediate assertion. But you may have to repeat much of the procedural RTL code to get the assertion to trigger properly.
 

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