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If you are asking verilog to spice conversion then this can be done using v2lvs utility in mentor calibre. there must be free tools availaible but i haven't used them.
You can only transfer gate-level netlist from Verilog to psice.
RTL or behavioural cannot be transfered generatically to general purpose spice!
If your netlist is so, you can use SMASH simulator from Dolphin.
use hsim have utility called "v2s" convert verilog netlist to spice netlist , but you should give hsim
"subcircuit cell AND2 NOT spice file first"
and convert to spice , you can use hspice ot hsim simulation it .
smash/ aditspice can combine spice + verilog simulation
if you never get cell spice file .
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