Why drive your external clock through a PLL?

I'm looking into an FPGA design in which 2 clocks external clocks are driven into a PLL that has been instantiated by the designer himself.
The outputs of the PLL are 2 clock signals of the same frequency.

What is the motivation behind such an approach?
Why not use the external clocks directly?

shaiko said:

I'm looking into an FPGA design in which 2 clocks external clocks are driven into a PLL that has been instantiated by the designer himself.
The outputs of the PLL are 2 clock signals of the same frequency.

What is the motivation behind such an approach?
Why not use the external clocks directly?

Click to expand...

50% duty cycle ?
Deskewing ?

A major challenge in a FPGA is clock distribution throughout the entire chip in a predictable way with a minimum of "skew" or difference in timing from one place to another. Meeting this challenge is the role of "clock management". An important tool used in clock management is the PLL. PLLs are used in various ways on different devices. One of the major ways they are used is to compensate for delays in the clock across the chip or from an input pin into the core of the chip. A straight path from an input pin to the clocks on logic elements in different places on the chip would have different delays if some means was not used to compensate for these delays. If these different delays were not adjusted, the maximum frequency of the clock would have to be limited. Using various clock management techniques allows for higher operating frequencies.

A PLL can also provide other useful clock functions which can be found in higher end FPGAs. For example, the input clock frequency can be divided down or even multiplied up. Multiple phase clocks can be produced. Take a look at the options available for your PLL function to get an idea of what can be done. The device data sheet should also have such details.

You may get more exact responses if you posted the part number or type of the FPGA you are using. Again, they are used in many ways on different parts.

Here is a description of a PLL function for an Altera device to give an example of some of the possible functionality:

"Parameterized phase-locked loop (PLL) megafunction. The altpll megafunction enables PLL circuitry, which is used to synthesize a clock signal that is based on a reference clock. The altpll megafunction can reduce clock delay and skew, and can be used to generate internal clocks that operate at frequencies that are multiples of the clock system frequency. The altpll megafunction can also improve setup and hold times. The Cyclone, Cyclone II, Cyclone III, Stratix, Stratix II, Stratix III, and Stratix GX PLLs can simultaneously multiply and divide the reference clock, provide an arbitrary phase shift, provide an external clock, and synchronize via an external feedback input. This megafunction is available for supported device (Arria II GX, Arria GX, Cyclone, Cyclone II, Cyclone III, HardCopy, HardCopy Stratix, Stratix, Stratix II, Stratix II GX, Stratix III, Stratix IV, and Stratix GX) families."

Jitter removal?

Analog Ground,
Thanks for the response.
But aren't clock pins strategically placed on the device to minimize the effect of clock skew?

TrickyDicky,
How does the use of a PLL reduce jitter?
Won't the PLL's output be as jittery as the oscillator that drives it?

shaiko said:

Analog Ground,
Thanks for the response.
But aren't clock pins strategically placed on the device to minimize the effect of clock skew?

TrickyDicky,
How does the use of a PLL reduce jitter?
Won't the PLL's output be as jittery as the oscillator that drives it?

Click to expand...

Selecting a pin location only gets so much. The signal still has to go to many places on the chip. Keep in mind that clock frequencies in current and next generation devices are approaching and exceeding 1GHz. Also, signals travel over metal pathways which are not simply short, metal wires. Resistive and capacitive effects cause delay and skew. Getting the clock through the input circuitry is also slow. Pin location does not help much for these issues.

As clock frequencies increase, other features offered by PLLs become more important. For example, clock frequency multiplication allows an internal clock to be much faster than the external clock which may be limited by having to travel through the PCB and into the chip.

PLL with loop filter is often called jitter cleaner. By choosing the right loop bandwidth and manipulating the lock detection window you can achive much lower jitter on output. Ofc as long as clock jitter is much bigger then VCXO noise floor.