Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

what's systemC and systemverilog

Status
Not open for further replies.
T

tybhsl

Member level 1
Joined
Dec 14, 2004
Messages
39
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
486
In some lettes, they often use systemC and systemverilog? waht are they? Thanks.
 

systemc is a library added to c++,could do system modeling.
system verilog is a new language for design and verification.
 

SystemC and Systemverilog are new developments in ASIC field . these develpoments mainly enhance system and ASIC verification features
 

Both are beneficial for System level modelling.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top