phuang
Junior Member level 1
Hi everybody,
I am puzzled with the cache decay (ISCA01, Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power) and DRG cache (DAC02- DRG-Cache: A Data Retention Gated Ground Cache for Low Power). The former said that the gated ground SRAM lost data, while the latter said the gated-ground SRAM can hold the data when turning off the sleep transistor. Tow opposite answers!
I tried in PTM 32nm, and found the SRAM can hold the data when I turned off the nMOS sleep transistor, and the "0" node saturated at about 340mV, just as the DRG-Cache.
My questions is that why people referred 617 times to the cache-decay paper (ISCA01, Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power) . Should I doubt all the people ?
Can anybody help me? Thank you very much!
Best,
Phuang
I am puzzled with the cache decay (ISCA01, Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power) and DRG cache (DAC02- DRG-Cache: A Data Retention Gated Ground Cache for Low Power). The former said that the gated ground SRAM lost data, while the latter said the gated-ground SRAM can hold the data when turning off the sleep transistor. Tow opposite answers!
I tried in PTM 32nm, and found the SRAM can hold the data when I turned off the nMOS sleep transistor, and the "0" node saturated at about 340mV, just as the DRG-Cache.
My questions is that why people referred 617 times to the cache-decay paper (ISCA01, Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power) . Should I doubt all the people ?
Can anybody help me? Thank you very much!
Best,
Phuang