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Xilinx spartan6 got DSP48A1 which is a 18-bit multiplier that can be chained to get wider input/output ( u can read more [example page 29] https://www.xilinx.com/support/documentation/user_guides/ug389.pdf). Altera got the same options for their DSP blocks, so basically any FPGA with at least 2 DSP units can do it.
Yep most of the Spartan 3/6 family have 18 bit multipliers primitives built into the silicon. There is normally a table with the number CLBs, IO pads and 18x18 multipliers is on the first or second page of the family datasheet for spartan 3 or 6. Perhaps the Virtex FPGAs have bigger multipliers that would be faster / more efficient than chaining 18-bit ones together although the cost is a lot higher.
To use the multipliers together you can simply use the CORE Generator IP wizard available in the free version of Xilinx ISE (webpack). This allows you to set the input width and output width to 32 bits / 64 bits respectively and configure things like working with signed or unsigned numbers or strobes to indicate when a multi-cycle operation is complete. The wizard will report how many 18x18 multipliers it requires to perform the specified function, and can additionally use CLBs to make up for the rest, although this will exhaust your combinational logic resources very quickly...
Note: if you want to work with floating point numbers, I believe there is a separate IP core that implements FPU functions like addition / division etc etc (also free in ISE). This will also use the 18x18 multiplier primitives automatically.
Actually, given the requirements you've listed, pretty much any FPGA will be able to handle this.
If you need to be able to input and output all 128 bits of data in parallel, then you'll want one that has at least 128 I/O pins. If you have a high data rate requirement, you might need to consider a device with hardware multipliers that can be chained in a way to achieve the precision you require. Really, you can do 32*32 multiplication on a 50 cent 8-bit microcontroller if you shift data in and out serially and don't need to do millions of operations per second.
Your question is a bit like asking "I need a car that will drive 100 kilometres".
Yep most of the Spartan 3/6 family have 18 bit multipliers primitives built into the silicon. There is normally a table with the number CLBs, IO pads and 18x18 multipliers is on the first or second page of the family datasheet for spartan 3 or 6. Perhaps the Virtex FPGAs have bigger multipliers that would be faster / more efficient than chaining 18-bit ones together although the cost is a lot higher.
To use the multipliers together you can simply use the CORE Generator IP wizard available in the free version of Xilinx ISE (webpack). This allows you to set the input width and output width to 32 bits / 64 bits respectively and configure things like working with signed or unsigned numbers or strobes to indicate when a multi-cycle operation is complete. The wizard will report how many 18x18 multipliers it requires to perform the specified function, and can additionally use CLBs to make up for the rest, although this will exhaust your combinational logic resources very quickly...
Note: if you want to work with floating point numbers, I believe there is a separate IP core that implements FPU functions like addition / division etc etc (also free in ISE). This will also use the 18x18 multiplier primitives automatically.
Afaik all synthesisors are clever enough to infer the correct sized multiplier from:
a <= b*c;
without having to resort to coregen. This will be fine for lower speed projects, but if you need a >300MHz clock speed, you'll probably want the efficiency gains you get from explicity instantitating a multiplier (in altera or xilinx)
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