Poly cap missing problem

1. If there is no poly cap, then poly ends (up/down) will align with diffusion edges. Why it is not done? What problem it might create?
2. If poly is smaller than the diffusion (device) width, what problem it might cause?

For reference please see the picture.

VLSI_Learner said:

1. If there is no poly cap, then poly ends (up/down) will align with diffusion edges. Why it is not done? What problem it might create?

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The first mask is the active (TOX) definition mask. In order to compensate for possible displacement between this previous active and the following poly gate masking, there's a finite overlap of poly necessary (and stipulated by design rules), called poly cap.

S/D (NMOS and PMOS) formation by diffusion or implant is a self-aligned process, i.e. (additionally to the NMOS or PMOS mask) masked by the poly gate. The a.m. poly cap also considers a small under-diffusion or -scattering (which also decreases the effective channel length below the drawn length).

VLSI_Learner said:

2. If poly is smaller than the diffusion (device) width, what problem it might cause?

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Obviously a (partly) continuous n+ or p+ region would be created, shorting S and D.

I can't get the idea of S/D shorting. Please explain.

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So you mean that poly cap is only needed for poly and S/D alignment as it's a self aligned process? But the alignment occurs along the length, not along the width. So again can't get the idea properly.

VLSI_Learner said:

I can't get the idea of S/D shorting. Please explain.

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Hope I can make it clear with the help of this shorted nMOSFET:

VLSI_Learner said:

So you mean that poly cap is only needed for poly and S/D alignment

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Poly cap - also called poly extension or poly overhang - is needed against mis-alignment between active area (thin oxide definition) and poly, and the later following S/D implant.

VLSI_Learner said:

... as it's a self aligned process? But the alignment occurs along the length, not along the width. So again can't get the idea properly.

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I think you're mixing up two different alignment occurrences: self-alignment and (possible) mis-alignment. Both are concerned:

Right: self-alignment regarding the channel formation concerns the length of the channel. The poly cap, however, is necessary to avoid the situation shown in the image above: if there were a mis-alignment between the active area (thin oxide definition) mask and the poly mask (in the direction of the channel's width), without the poly extension an S/D shorting could occur.

Hope I could make this clear now. You might perhaps want to read the explanation given in , see Poly extension from diffusion on p. 32 (p. 38 of the PDF) .

Thank you. I understood your explanation. But there is a small thing that is bothering.
During fabrication first two diffusion layers are drawn, but they are placed some distance apart (channel). And on top of that spacing between two active areas poly (here short poly than the diffusion width) is deposited. So basically there should not be any short between S/D region. So I guess only the device width reduces.

I think you misunderstand the order and significance of the mask steps, sorry. I try to make this clear, leaving out the (many) intermediate steps, which aren't necessary for understanding the MOSFET formation process. Only valid for self-aligned gate processes:

1. Active Mask: Definition of the thin oxide (TOX) regions for all MOSFETs (NMOS & PMOS)
2. Poly Mask: Defines all poly gates (and poly capacitors) over TOX, poly gate extensions, poly connections and poly resistors over field oxide (FOX)
3. N+ S/D Mask: coincides but overlaps all TOX regions for NMOSFETs
4. P+ S/D Mask: coincides but overlaps all TOX regions for PMOSFETs

Below pls. find a process layout tutorial by Ken Martin which might help for understanding. See slides 9-12 for the a.m. self-aligning gate process. Slide 16 shows possible misalignment problems: View attachment 02_processing_layout.pdf

Well, my mistake. Poly is created first and then S/D region is created.
But is there only one mask for S and D region. And poly edge decides the channel-wise spacing between S/D region. Am I right?

VLSI_Learner said:

... is there only one mask for S and D region. And poly edge decides the channel-wise spacing between S/D region. Am I right?

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Yes - yes - yes. Finally understood, congratulations! ;-)

Thanks a ton, eriki...

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Thanks a ton, eriki...