eda_wiz
Advanced Member level 2
Currently I use power compiler to do post layout power esimation of my block.
ie use the SOCE netlist and do post layout simulation to generate vcd/saif.
annotate the vcd/saif to power compiler along with the netlist, sdf to report power.
is there any more accurate method apart from doing spice?
thanks
ie use the SOCE netlist and do post layout simulation to generate vcd/saif.
annotate the vcd/saif to power compiler along with the netlist, sdf to report power.
is there any more accurate method apart from doing spice?
thanks