question about Cadence Virtuoso-Spectre monte carlo analysis

Hi everyone,

Previously I used PSPICE for my analog/mixed-signal simulations. Recently I tried to convert my design to Cadence Virtuoso-Spectre. I have been self-studying it for a few days. It is quite different from PSPICE and it looks like powerful and complicated. Due to lack of training materials I have to google online or look at the HEP manual installed with the software.

Here I have a simple question regarding monte carlo analysis using ADE XL. Here is my procesure:

1) Capture design (a inverter) in schematic editor. Then from there, launch -- ADE L

2) In ADE L, I setup the simulator, library, variables, output, and analysis. I can run simulations (tran, DC) successfully.

3) next I want to do a monte carlo analysis. I know I have to start ADE XL for the monte carlo analysis. Basically I want to see how the model parameter (VTO) variation changes the circuit performance. In my technology library folder, I noticed there is a mc folder along with other folders (tm, ws, wp, wz, wo). I guess this mc folder is used in the monte carlo analysis.

My question is how do I use the models in the mc folder to specify lot variation and device mismatch variation?

In PSPICE it is very straight forward. I just put dev and lot statement after the parameter I want to vary then it is ok to go. But how to do it in ADE XL environment?

Is there any detailed tutorial available somewhere in this forum?

Thanks for your help!

Did you find this one?

Hi erikl,

Thanks for your help! I studied the tutorial in your attachment and I also did some research on our foundry website. Finally I got the monte carlo simulation work.

The way Cadence Spectre does monte carlo analysis is different from PSPICE. In PSPICE one needs to figure out the process and mismatch variations by himself by looking at the technology process spec (for LOT, or process) and the transistor area in your design (for DEV, or matching). Then modify the transistor models accordingly.

In Spectre, a special model file has to be prepared for this purpose and Spectre calculates the process and mismatch automatically based on the sigma you specified and the transistor size on the schematic. Our foundry has already provided the model file for monte carlo in Spectre. I just need to point to this model file and specify the section and input the sigma value. Then I am able to run Monte Carlo analysis and see plots after that.

Hi sean,

thanks for your feedBack! Sure: mismatch doesn't depend on device size only, but also on the fabs/foundries process management (and how many sigmas they test & release to the customers). With a fab/foundry PDK you usually receive the appropriate data. AFAIK there are no PSPICE PDKs, so you would have to collect appropriate variation sigmas from other sources.