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Regarding Toplogy and placement in DDR ???

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Hi everyone,

Right now in my design i am MCF548x ColdFire® Microprocessor using before placing the processor and ddr i need to clarify some thing

what is topology ?? topology is very depends on placement ??
who will decide topology (hardware designer or pcb designer )

which topology is best for ddr board ?

i have the reference document but i could not find answer

i need help from anyone......!
 
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The topology in this case generaly refers to how the processor interfaces with the memory and how that memory is arranged, seperate devices, SIMMs, number of devices etc etc. The Engineer will decide the generic topology then you lay the board out using all the numerous guidlines to fulfill that topology. Some topology require VTT pull up resistors some require other things.
 
Hi Marce,

Thanks for your reply.after the place the processor what should i need to place .

i red some guideline regarding my design they prefer flyby topology why ??
 
hi marce,

my design has MCF548x ColdFire® Microprocessor,VME connector,FBGA programmer for VME ,IO signal,DDR SDRAM using .my hardware designer advice to me to place the components as the follow diagram
i have several question in that
why sdram should be near to place programmer ??
if i place the flash memory next to the programmer what will happen ??
please reply .....

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It all depends on speed of the memory device if your sdram is more faster then your flash memory you have to place more near to processor.
 

Hi praveen,

thanks for your reply SRAM placement is common for all or it will be vary depends on application ?? how much distance i need to keep the sram from programmer IC
if you have any document regarding sdram please post it
 

Use this topology..
**broken link removed**
Regards..
Praveen
 

Hi praveen,
thanks for your answer
totally how many topology is available ?? it is ddr sdram board but in that document contain the ddr3 only. it will be support ddr also;
 

Use some Signal integrity tool to decide constraints and topology based on your application and operating frequency..It should be decided by the hardware circuit designer or Signal integrity engineer..
 
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hi siva,
Thanks for your reply. is it possible to set the constraint using document (Micron hardware point to point document ),with out help of hardware or signal integrity engineer is not possible to complete ddr X board
 

We can,but better to simulate and see the results if your topology is complex..
 

my design has MCF5485CVR200 which is connect to ddr sdram how much distance i need to keep ddrsdram tp MCF5485CVR200 processor ??

 

Looks like topology is complex,it is not point to point.You can use the attached topology for address bus and data bus is point to point,regarding lengths you need simulate to get the better result with the termination on address at junction point...
 

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Hi siva,
Thanks for your reply

As you given the topology mention ddr sdram should place top and Bottom ,in case if i place i could not route differential pair right ??
for length matching also i may be get problem
for example,address line (marked in blue color ) could not do the length matching right ??
like that differential signal (white color ), yellow color -data signal,
green color for data strobe
length matching may be get problem i think so .... check image

- - - Updated - - -

 
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Total lack of infomation and many confusing contributions...

MCF5485CVR200 is supporting DDR(1) only. Pointless to discuss DDR3 routing requirements.

You've been asking about SDRAM but mentioned only a SRAM part number CY62157EV30LL.

First point would be to clarify the actually intended memory configuration: SRAM only or SRAM + (DDR)SDRAM?
 

Looks like ur data bus is not point to point?Is it correct?

If it is point to point then follow below points,otherwise ignore it.

Place components one above other (top & bottom).
Routing is not possible with two layers.you need to use multilayer for DDR routing..
Routing topology is star.
Length matching is possible.Make sure that arms from star point should be matched properly

refer below link for guidelines...

https://cache.freescale.com/files/3...ALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation
 
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