What are the different approaches for counter design?

• Nov 18, 2004

• #1

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carrot

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vhdl code for decade counter ic 7490

hi

Can any one of you tell what are the different approaches for counter design. I do not want the types of counter like mod2,mod4...... . I want what r the ways in which this counter can be done. If possible give me a good link.

 

• Nov 18, 2004

• #2

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brmadhukar

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synchronous counter 10ghz

Hi,
You may use a state Machine approach for counter design. You define what are the next states and then genrate the circuit based on the type of flip flop you want to use?

B R
Madhukar

Ref: An engineering approach to digital design -- William Fletcher

 

• Nov 21, 2004

• #3

V

videohu

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Counter design

Basic component of counter is gate. If you want to know detailed structure, you can refer to microelectrical related books, there are detailed information.

 

• Nov 22, 2004

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Counter design

actually, how many approaches are there to design a divide by n counter?

 

• Nov 22, 2004

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djalli

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Re: Counter design

Edward_2288 said:

actually, how many approaches are there to design a divide by n counter?

Click to expand...

Depends how do you want to look at it. There are many ways. I am putting a figure using 7490 decade counter IC.

 

• Nov 22, 2004

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flatulent

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Re: Counter design

There are two basic ways to divide by N. The digital logic methods described above use storage elements such as latches and feedback paths to make a state machine. They have the property of holding the value when the clock is removed.

There is another way that is all analog. The signal to be divided is applied to a mixer. The output is the desired frequency. A part is split off and multiplied by N-1 which is put into the other mixer input. This idea goes back over 60 years. It produces the lowest phase noise of any division method. It costs a high amount (money and power consumption and volume/weight) though.

 

• Nov 23, 2004

• #7

djalli

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Re: Counter design

flatulent said:

There is another way that is all analog. The signal to be divided is applied to a mixer. The output is the desired frequency. A part is split off and multiplied by N-1 which is put into the other mixer input. This idea goes back over 60 years. It produces the lowest phase noise of any division method. It costs a high amount (money and power consumption and volume/weight) though.

Click to expand...

And is far more complex then buying counter ic's. right?

flatulent the second method, is fancy and complex, is employed what I think is of fully developed commercial entities and of course army reseach projects maybe (they have plenty of money) using this method.
I believe he wants it for school lab work/project.

flatulent thank you for the second method. I learned something new today.

 

• Nov 23, 2004

• #8

flatulent

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Re: Counter design

Correct. The all analog way is much more expensive than buying a counter IC. However it is the only way if you want the lowest possible phase noise in your system or if the system operates above 10 GHz or so where the low cost counters such as from Hittite IC company stop working.

 

• Nov 27, 2004

• #9

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Re: Counter design

Here's a diagram the clever analog frequency divider (R. L. Miller 1939) that flatulent is describing. It's not a counter.

Image shamelessly snitched from this paper: https://icd.el.utwente.nl/publications/get_file.php?pub_id=173

 

• Nov 29, 2004

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Re: Counter design

counter design can be done by using a state machine approach if u r designing a synchronous counter.for ripple counter u can refer to digital logic design by
holdsworth and woods.

 

• Jan 12, 2005

• #11

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Re: Counter design

could i ask a question....

if we write the VHDL code for state machine or any other digital system design....how do v c the synthesize circuits....or how do v get the picture of the logic gates design....

i m using max+plus II.....i cannot find any option to c the synthesize output by the vhdl code.....


thanxs in advance.....

 

• Jul 6, 2007

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Re: Counter design

how do we simulate/measure the phase noise contribted by the divider?

How the Values of N ( Counter value) affects the Phase noise.

Pls reply

Thanks & regards
SavithRu

 

• Jul 6, 2007

• #13

lordsathish

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Re: Counter design

The best way would be to go with flip flops... first write down the sequence that you have to count... then find out the transition in each outputs at each stage...
for the flip flop that you gonna use find out the combinational input based on their transistion tables... all text books deal with such approach only...

 

• Jul 9, 2007

• #14

ahmad_abdulghany

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Counter design

How're you going to implement it? Using discrete components or will implement it in an IC ?

 

• Jul 10, 2007

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Re: Counter design

Steps for designing a counter(for synchronous conunter)

write down the sequence , couter must follow..
Select the flip flop u want to use..
Write the flip flop exitation table and using K map, find how to connect the output of one FP to another.....

Take care that , the counter is not entered to undefined states....

 

• Aug 5, 2007

• #16

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Re: Counter design

Any sequential circuit can be designed by state machine approach..
For a counter, after the state machine flow, it can be designed using any one of the four types of flipflops(D ff, T ff, JK ff, RS ff)