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Help! it's urgent! (VHDL) ncsim error:signal "p" has multiple sources

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sheepherdee

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I'm a beginner.When I complie this VHDL file of my IC design homework, I encounter with the error. I have searched many forums and know the reasons now. But I don't know how to make it right. If anyone can help me, I really appreciate. At last, thank you.

error:signal "p" has multiple sources

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
entity fsq is
port
(
clk : in std_logic;
u   : out std_logic
);
end fsq;
 
architecture afsq of fsq is
signal p  : std_logic_vector(3 downto 0);
signal p0 : std_logic;
signal p1 : std_logic;
signal p2 : std_logic;
signal p3 : std_logic;
 
begin
 
process(clk)
begin
if clk'event and clk='1' then
p0<=not p0;
end if;
end process;
 
process(p0)
begin
 
if p0'event and p0='0' then
p1<=not p1;
end if;
end process;
 
process(p1)
begin
if p1'event and p1='0' then
p2<=not p2;
end if;
end process;
 
process(p2)
begin
if p2'event and p2='0' then
p3<=not p3;
end if;
end process;
 
p<=p3&p2&p1&p0;
 
process(p)
begin
 
if p="1000" then
p<="0000";
end if;
 
case p is
when "0000" => u<='0';
when "0001" => u<='1';
when "0010" => u<='1';
when "0011" => u<='0';
when "0100" => u<='1';
when "0101" => u<='1';
when "0110" => u<='1';
when "0111" => u<='1';
when others => null;
end case;
 
end process;
end afsq;


THANK YOU
 
Last edited by a moderator:

sheepherdee said:
I'm a beginner.When I complie this VHDL file of my IC design homework, I encounter with the error. I have searched many forums and know the reasons now. But I don't know how to make it right. If anyone can help me, I really appreciate. At last, thank you.

error:signal "p" has multiple sources

p<=p3&p2&p1&p0;

process(p)
begin

if p="1000" then
p<="0000";
end if;


THANK YOU
Click to expand...

Just like the error message says, you have multiple sources driving signal p. You are assigning values to p in two different places.
 

The problem can be easily handled by moving both assignments inside the same process.

By the way, does your homework problem ask for a ripple counter? A synchronous counter would be better.
 
thank you ！
we don't specify the type of the counter.
 

we don't specify the type of the counter
Click to expand...
A ripple counter uses the output of one flip-flop as clock for the next stage. As a result, each stage gets an additional delay related to the preceeding and and the output bits toggle at different times. This causes glitches in the decoded output and limits the maximum counter frequency.

A synchronous counter uses the same clock for all flip-flops and more complex logic for the D input of each flip-flop. It's the preferred way to design a counter in programmable logic or ASIC.

It's easy to write a synchronous counter in VHDL
Code: 
signal p: unsigned[2 downto 0];
...
process (clk)
if clk'event and clk='1' then
  p<=p + 1;
end if;
end process;

Another comment on the design. The state "1000" is only transient and can be omitted as well as p3. A binary counter will count from "111" to "000" without additional logic.
 
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