cyboman
Member level 4
I'm trying to understand how Z and X states are synthesized in Verilog, if they are at all.
Lets say I have the following circuit:
My question is how will the actual circuit determine that input is in the Z state? As far as I understand simulators can understand Z state but in the real world Z is when the input is floating. So the circuit actually can't determine if one of its inputs is in the Z state. What I think is going to happen is that whatever state the input was before (1 or 0) going to Z state is going to be preserved on the input when it goes to the Z state. As far as X state, this state is unsynthesizable since in real world input is always going to be a 0 or a 1. Am I correct?
Any help is appreciated.
Lets say I have the following circuit:
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 case(sel) 2'bzz : begin out = a; end 2'b0z : begin out = b; end 2'b1z : begin out = c; end 2'bz0 : begin out = d; end 2'bz1 : begin out = a; end 2'b00 : begin out = b; end 2'b01 : begin out = c; end 2'b10 : begin out = d; end 2'b11 : begin out = a; end default : begin out = b end endcase
My question is how will the actual circuit determine that input is in the Z state? As far as I understand simulators can understand Z state but in the real world Z is when the input is floating. So the circuit actually can't determine if one of its inputs is in the Z state. What I think is going to happen is that whatever state the input was before (1 or 0) going to Z state is going to be preserved on the input when it goes to the Z state. As far as X state, this state is unsynthesizable since in real world input is always going to be a 0 or a 1. Am I correct?
Any help is appreciated.
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