are Z and X states synthesizable in Verilog

[cyboman]

I'm trying to understand how Z and X states are synthesized in Verilog, if they are at all.

Lets say I have the following circuit:

---

Code Verilog - [expand]
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case(sel)
     2'bzz : begin 
                 out = a; 
               end
     2'b0z : begin
                 out = b; 
               end
     2'b1z : begin  
                 out = c;
               end
     2'bz0 : begin  
                 out = d;
               end
     2'bz1 : begin  
                 out = a;
               end
     2'b00 : begin  
                 out = b;
               end
     2'b01 : begin  
                 out = c;
               end
     2'b10 : begin  
                 out = d;
               end
     2'b11 : begin  
                 out = a;
               end
 
     default : begin
                  out = b
                end
endcase

---

My question is how will the actual circuit determine that input is in the Z state? As far as I understand simulators can understand Z state but in the real world Z is when the input is floating. So the circuit actually can't determine if one of its inputs is in the Z state. What I think is going to happen is that whatever state the input was before (1 or 0) going to Z state is going to be preserved on the input when it goes to the Z state. As far as X state, this state is unsynthesizable since in real world input is always going to be a 0 or a 1. Am I correct?

Any help is appreciated.

 

[FvM]

So the circuit actually can't determine if one of its inputs is in the Z state.

Right. Z is only synthesizable on outputs. X is supported for definition of don't care.

Although not necessarily implemented by all synthesis tools, IEEE 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis gives a general idea about X and Z support.

5.5 Support for values x and z

The value x may be used as a primary on the RHS of an assignment to indicate a don’t care value for synthesis.

The value x may be used in case item expressions (may be mixed with other expressions, such as 4’b01x0) in a casex statement to imply a don’t care value for synthesis.

The value x shall not be used with any operators or mixed with other expressions.

The value z may be used as a primary on the RHS of an assignment to infer a three-state driver as described in 5.4.

The value z (or ?) may be used in case item expressions (may be mixed with other expressions, such as 4’bz1z0) for casex and casez statements to imply a don’t care value for synthesis.

The value z shall not be used with any operators or mixed with other expressions.

 

[cyboman]

So as far as my code goes, the inputs containing z will be considered as don't care. Am I correct?

 

[FvM]

I'm not very familiar with these constructs, but according to the linked standard excerpt, z would be used with casez. You should check in addition, if the constructs are supported by your synthesis tool. In my view, there's no particular purpose to use z state for don't care constructs in synthesizable Verilog, in so far the question is somehow academic.