er.akhilkumar
Full Member level 2
Hello All,
I am trying to simulate a System C top in which VHDL component is instantiated. File has been compiled successfully but a NCELAB error is reported during elaboration.
Error:
ncelab: *F,SCIPCF: Could not connect port 'port_0' for instance 'sctop.or_gate'.
ncsc_run: *E,TBELABF: ncelab returned non-zero exit status
Following is code:
VHDL component : or_n :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or_n IS
GENERIC (
P_WIDTH : integer := 2
);
PORT (
a : IN std_logic_vector(P_WIDTH-1 downto 0);
z : OUT std_logic
);
END or_n;
ARCHITECTURE rtl OF or_n IS
BEGIN
func_or:
PROCESS (a)
VARIABLE z_v : std_logic;
BEGIN
z_v := '0';
FOR i IN 0 TO P_WIDTH-1 LOOP
z_v := z_v OR a(i);
END LOOP;
z <= z_v;
END PROCESS func_or;
END rtl;
Foreign class for VHDL component:
class or_n : public ncsc_foreign_module {
public:
sc_in< sc_lv<8> > a;
sc_out<sc_logic> z;
or_n ( sc_module_name nm, int i) :
ncsc_foreign_module (nm),
G_WIDTH (i) {
cout << "Setting width to " << G_WIDTH << endl;
ncsc_set_hdl_param ( "P_WIDTH" , G_WIDTH) ;
}
SC_CTOR(or_n) : a("a"), z("z") { }
const char* hdl_name() const { return "or_n"; } // NC mode name
~or_n () {}
private:
int G_WIDTH;
};
Top class : sctop
SC_MODULE(sctop) {
public:
SC_CTOR(sctop): port1("port1"), port2("port2"), or_gate("or_gate", 8) {
or_gate.a(port1);
or_gate.z(port2);
}
protected:
sc_signal< sc_lv<8> > port1;
sc_signal<sc_logic> port2;
or_n or_gate;
};
NCSC_MODULE_EXPORT(sctop)
Command:
ncsc_run -dynamic or_n.vhd or_n.cpp sctop.cpp -top sctop
Can anyone please help me out solving this problem?
Thanx
I am trying to simulate a System C top in which VHDL component is instantiated. File has been compiled successfully but a NCELAB error is reported during elaboration.
Error:
ncelab: *F,SCIPCF: Could not connect port 'port_0' for instance 'sctop.or_gate'.
ncsc_run: *E,TBELABF: ncelab returned non-zero exit status
Following is code:
VHDL component : or_n :
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or_n IS
GENERIC (
P_WIDTH : integer := 2
);
PORT (
a : IN std_logic_vector(P_WIDTH-1 downto 0);
z : OUT std_logic
);
END or_n;
ARCHITECTURE rtl OF or_n IS
BEGIN
func_or:
PROCESS (a)
VARIABLE z_v : std_logic;
BEGIN
z_v := '0';
FOR i IN 0 TO P_WIDTH-1 LOOP
z_v := z_v OR a(i);
END LOOP;
z <= z_v;
END PROCESS func_or;
END rtl;
Foreign class for VHDL component:
class or_n : public ncsc_foreign_module {
public:
sc_in< sc_lv<8> > a;
sc_out<sc_logic> z;
or_n ( sc_module_name nm, int i) :
ncsc_foreign_module (nm),
G_WIDTH (i) {
cout << "Setting width to " << G_WIDTH << endl;
ncsc_set_hdl_param ( "P_WIDTH" , G_WIDTH) ;
}
SC_CTOR(or_n) : a("a"), z("z") { }
const char* hdl_name() const { return "or_n"; } // NC mode name
~or_n () {}
private:
int G_WIDTH;
};
Top class : sctop
SC_MODULE(sctop) {
public:
SC_CTOR(sctop): port1("port1"), port2("port2"), or_gate("or_gate", 8) {
or_gate.a(port1);
or_gate.z(port2);
}
protected:
sc_signal< sc_lv<8> > port1;
sc_signal<sc_logic> port2;
or_n or_gate;
};
NCSC_MODULE_EXPORT(sctop)
Command:
ncsc_run -dynamic or_n.vhd or_n.cpp sctop.cpp -top sctop
Can anyone please help me out solving this problem?
Thanx