olaf01555
Newbie
Hi All,
I am having a analog circuit in my schematic editor and I instantiated a symbol (created it using VerilogIn from rtl code).
Now when I was trying to run Cadence ams simulation I was getting an error.
I can able to run ams simulations successfully with veriloga, But I am not sure why I was not able to run using rtl code.
Any inputs...
I am having a analog circuit in my schematic editor and I instantiated a symbol (created it using VerilogIn from rtl code).
Now when I was trying to run Cadence ams simulation I was getting an error.
I can able to run ams simulations successfully with veriloga, But I am not sure why I was not able to run using rtl code.
Any inputs...