sonofflynn
Junior Member level 2
I am currently having an issue with ncelab when using ncverilog in Virtuso. I keep getting error messages like the following:
nfetx M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),
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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.
nfetx M2 ( .S(cds_globals.gnd_), .G(B), .D(hnet14),
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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,20|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M2' of design unit 'nfetx' is unresolved
Here is what I did:
I synthesized a design with Design Compiler and then imported the verilog netlist into Virtuoso to create a schematic. Next, I opened NC-Verilog in Virtuoso and selected the schematic as the top level design. I initialized and generated the netlist for the design. However, I run into problems when I try to simulate.
nfetx M1 ( .S(cds_globals.gnd_), .G(net11), .D(Y),
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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,18|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M1' of design unit 'nfetx' is unresolved in 'worklib.AND2X1:verilog'.
nfetx M2 ( .S(cds_globals.gnd_), .G(B), .D(hnet14),
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ncelab: *E,CUVMUR (./ihnl/cds0/netlist,20|8): instance 'test.top@counter<module>.U31@AND2X1<module>.M2' of design unit 'nfetx' is unresolved
Here is what I did:
I synthesized a design with Design Compiler and then imported the verilog netlist into Virtuoso to create a schematic. Next, I opened NC-Verilog in Virtuoso and selected the schematic as the top level design. I initialized and generated the netlist for the design. However, I run into problems when I try to simulate.