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set_input_delay to output pins

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skyworld_cy

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Hi,

in which case can one set_input_delay to output pins? I just met a case: In top level there are two submodules, I just found the scripts set_input_delay to one of submodules' output pin. Can anybody help me to understand this?
 

If it is a pure combinational path only
 

if I name register on the left of combo logic as reg_left, and the other as reg_right. Do you mean I should do set_input_delay to reg_left/Q? If this is right, does this mean the input delay set to reg_left is in fact the output delay of reg_left? And is it syntax right in DC to set_input_delay to an output pin? thanks
 

Ideally if you go by my picture You need to set input delay and output delay also to meet timing between Left Reg --> to --> Right Reg
 

of course I should write all timing requirements. But is it correct to set input delay to the register left?
 

input delay and output delay related to your module. Leftand Right registers does not come into picture.
 

Why you are confused How can constraints defined for other modules You have to define constraints for your module.
 

Is there anybody else could give me some help? thanks
 

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