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FIR filter internal bit growth

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H.Hachem

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Hello,

I'm trying to implement an FIR filter in Verilog and was wondering, if there's any practical way to truncate/round the MAC outputs in order to get the same output bit length as the input. I would simply round the output of the filter to the nearest quantization level, but maybe someone has a better idea.
Ans how about when using multistages, e.g. CIC-CIC-FIR-CIC-CIC . Should I apply bit pruning to every CIC stage or simply round at the very end of the chain?

Thanks in advance
 

The resoluion and dynamic range of digital filter data path and coefficients must be designed according to filter specifications. Keeping the bit length across multiplications requires truncation (preferably with saturation logic) and rounding. In VHDL it's easily achieved by the fixed point package, in Verilog you can write functions for it.
 

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