Starting with FPGA, VHDL and Spartan 3A (6)

[carpenter]

Hello
I start with FGPA, precisely, Spartan 3A and Spartan 6 form Xilinx. http://www.files.em.avnet.com/files/...ev2_112008.pdf

You can recommend the tutorials, video courses and other resources for learning the issues.

[shaiko]

I see this board has an I2C temperature sensor.

Make it a project.
Write a VHDL I2C tx/rx device...

Consult this for your VHDL learning curve:
http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html

Also,
you can post your questions here as you progress

[carpenter]

OK her is several my question,

My first design , very simple RS Flip Flop with Q output and AND gate with x,y input.
VHDL code below.
Question.
1. How connect Q output RS FF with y input AND gate? (internal connect inside FPGA)
2. How connect on x input of AND gate clock from external differencial LVPRCL driver?
3. Is inside ISE any tool which say me how maximal frequency is applicable for this design inside Spartan 3A?

Thansk you

-----------------------------------------------
- RS Flip Flop -
-----------------------------------------------

entity RS is
port (reset, set: in std_logic;
q : out std_logic);
end RS;

architecture rtl of RS is
begin
process (reset, set) begin
if (reset = '0') then
q <= '0';
elsif (set = '0') then
q <= '1';
end if;
end process;
end rtl;

-----------------------------------------------
- AND GATE -
-----------------------------------------------

entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;

architecture behav of AND_ent is
begin
F <= x and y;
end behav;

[TrickyDicky]

1. You need to create another entity that instantiates both the and gate and the latch (its not a flip flop because it is not edge triggered)
2. in your new entity, you have an LVPRCL input that you will assign to the correct pin in your FPGA in your ISE project.
3. Yes. When you compile the design it should tell you the FMax for your design. Im not sure what the tool is called in ISE but there is one.