annotation problem after reading VCD file using primrtime-PX during power estimation

Hello all:

I am estimating power of a post-synthesis using a VCD based flow using Primrtime-PX. I am using following command for reading the vcd file:
read_vcd -rtl -strip_path tb_registerfile/UUT reg.vcd

and it is printing out the following messages to console

Information: Reading file reg.vcd to annotate toggle rates on the design...
======================================================================
Summary:
Total number of nets = 62693
Number of annotated nets = 61157 (97.55%)
Total number of leaf cells = 62586
Number of fully annotated leaf cells = 44154 (70.55%)
======================================================================


I have no clue about the percentages that the summary is showing. All my designs has 100% annotation. Could you please help me in understanding why the annotation percentage is not 100%.

Thanks for your time

Why are you using "-rtl " if you are using the vcd dumped out using the post synthesis netlist?

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Why are you using "-rtl " if you are using the vcd dumped out using the post synthesis netlist?

Thanks for your following your reply teja.I am new to this. I got confused and here is my understanding, please correct me if I am wrong :Since it is a gate-level netlist I shouldn't use -rtl option. following your suggestion I removed the -rtl, but still it has no difference.

Is that vcd file dumped using your post synthesis netlist or using the RTL file?

If you are using vcd file which is generated using the RTL file then definitely there are chances of some annotation issues, because some of the nets which are present in the RTL vcd may not be present in the post syn netlist due to logic optimization. Dump the vectors using the same netlist and your test bench and use it in the flow to get 100% coverage.

@teja The VCD file was sgenerated using the post-synthesis netlist only. Also this design is clock-gated and by listing the non-annotated nets using report_switching_activity, I came to know that most of the nets are related to clock-gating logic. Could you please explain why this is happening..

If both vcd and netlist are consistent you should not see any annotation issue.

grep in vcd the net which is not annotated.

Also, have you run legalize names before dumping the netlist?

@teja: if you are talking about change_names command, I am not using any change_names command. should I use it?