Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

The transfer curve of an inverter after changing Vdd and Vss

Status
Not open for further replies.

carrot

Full Member level 3
Joined
Feb 23, 2004
Messages
182
Helped
9
Reputation
18
Reaction score
4
Trophy points
1,298
Location
Bangalore, India
Activity points
1,532
Inverter

hi

What will be the transfer curve of an inverter if i change Vdd and Vss?
 

Inverter

If you change Vdd and Vss you will destroy the inverter.
 

Re: Inverter

ME said:
If you change Vdd and Vss you will destroy the inverter.

Not really. The inverter will become a degraded tranfer gate which the High signal will become Vdd-Vt
 

Re: Inverter

I fundamentally concur with "HCM_Bucat" but have additional information. One could call it a degraded buffer (incompletely trying to map the input state to the output state) if Vdd and Vss are reversed. And Vss is not necessarily ground, more specifically it is either ground or a negative supply (relative to Vdd).

The PMOS device in effect becomes a "pull-down" device and the NMOS device becomes a pull-up device, exactly the opposite of what they do best. The output can be pulled up to a maximum of |Vdd - Vth|, where Vth is the NMOS threshold voltage and [additionally] the output can be pulled down to no lower than Vtp (V threshold for the PMOS device) instead of zero.

Case 1
Input = 0, output = 0 + Vtp
Case 2
Input = 5V, output = |5V - Vth|
 

Re: Inverter

Does that means that this inverter can be used to limit the voltage swing?
 

Re: Inverter

golfbumb said:
I fundamentally concur with "HCM_Bucat" but have additional information. One could call it a degraded buffer (incompletely trying to map the input state to the output state) if Vdd and Vss are reversed. And Vss is not necessarily ground, more specifically it is either ground or a negative supply (relative to Vdd).

The PMOS device in effect becomes a "pull-down" device and the NMOS device becomes a pull-up device, exactly the opposite of what they do best. The output can be pulled up to a maximum of |Vdd - Vth|, where Vth is the NMOS threshold voltage and [additionally] the output can be pulled down to no lower than Vtp (V threshold for the PMOS device) instead of zero.

Case 1
Input = 0, output = 0 + Vtp
Case 2
Input = 5V, output = |5V - Vth|

Yes, You are correct !
 

Re: Inverter

lokeyh said:
Does that means that this inverter can be used to limit the voltage swing?
Maybe, I but don't know any application for this.
 

Re: Inverter

then o/p swing will reduces..also some substrate bias effect will come into picture..
 

Re: Inverter

carrot said:
hi

What will be the transfer curve of an inverter if i change Vdd and Vss?

It acts as weak buffer with reduced swing.... Noise margin will reduce.....
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top