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  1. #1
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    About Verilog and MATLAB

    Hi,
    1. Is there any way to convert Verilog code to MATLAB code?


    2. My program requires the following processes:
    - A verilog module is constructed in Xilinx
    - The requirement is to give input through MATLAB to the verilog code.
    - Then the outputs are got and waveform plots are to be done in MATLAB.
    How this can be done? I have already searched and found that Xilinx system generator is used to link simulink with xilinx... Can u clarify me with this?

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  2. #2
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    Re: About Verilog and MATLAB

    The Matlab code can be converted in Simulink and using the function makehdl() in MATLAB, this can be converted to vhdl coding. You can refer the Matlab help and i hope you will get some information.



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  3. #3
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    Re: About Verilog and MATLAB

    Check the "Importing HDL Modules" chapter in "System Generator for DSP User Guide" below. (By the way, download Xilinx Document Navigator to manage all Xilinx documents) :

    http://www.xilinx.com/support/docume...ysgen_user.pdf


    Quote Originally Posted by Taison37 View Post
    Hi,
    1. Is there any way to convert Verilog code to MATLAB code?


    2. My program requires the following processes:
    - A verilog module is constructed in Xilinx
    - The requirement is to give input through MATLAB to the verilog code.
    - Then the outputs are got and waveform plots are to be done in MATLAB.
    How this can be done? I have already searched and found that Xilinx system generator is used to link simulink with xilinx... Can u clarify me with this?
    Cheers,
    Jim



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  4. #4
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    Re: About Verilog and MATLAB

    use the file operations (fopen, fscanf) etc in Matlab to read and write the file in text
    and then use similarly file operations in Verilog to read and write from verilog ( readmemb= read from memory in binary); fopen ; fprintf etc...

    The way would be this...
    1) Matlab->write data to a text file(dnt exactly remember the command, search on google)
    2) Read from that text file and store to a memory in Verilog testbench using either readmemb or readmemh command
    3) then using clocks read from memory location
    4) after operation store in the text file using fdisplay command
    5) read from matlab..(google it :) ) ( i guess fscanf is used

    for verilog www.testbench.in is really good. go there and search for file read and write in verilog examples...
    When the going gets weird, the weird turn pro.
    H.S. Thompson



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