Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

problem in signed and unsigned variable

Status
Not open for further replies.
A

amir1985

Newbie level 3
Joined
Mar 6, 2012
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,298
hi every one!

how we can know the difference between two complementary and unsigned value in verilog code when we do subtraction that it's value can be both negative and positive numbers?
 

hello amir,

In Verilog 2001, you can now declare signed variable and it will automatically be 2's compliment signed variable.

Code: 
wire signed [7:0] inp1; //will take negative values as 2's compliment
reg signed [7:0] inp2; //will take negative values as 2's compliment

assign inp1 = 10000000; // It means -128 in two compliment

initial begin
inp2 = -5; //Verilog will itself give it the value of [B]8'b11111101[/B] i.e. signed -5
end

actually if you declare normal variables as well, you can assign negative values and it will be itself converted to
2's compliment, but of course since it is unsigned variable, it cannot be then used normally for 2's compliment
operations normally...

for further study read this link and search this Register Data type

AHHH also the MSB indicate the negatove or positive value i.e. it is the signed bit
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top