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  1. #1
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    How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 nano.

    Hi am trying to integrate a NIOSll processor in my already existing FPGA design so that finally i have a single FPGA solution.
    I have a signal monitoring unit designed in VHDL and i need to connect the created design to a NIOSll processor for my calculation and displaying the result.
    I have found ways to do things individually but i want both elements in single FPGA.
    Is is possible?
    If yes then please let me know how.
    Please look into the image. Part inside red is what i want to implement.


    Thanks in advance

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  2. #2
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    Re: How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 na

    Yes, it is possible. You can add your VHDL module as a IP to your NIOS II project. You can control/monitor the VHDL module by using GPIO access from NIOS.

    Gongdori



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  3. #3
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    Re: How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 na

    Thanks for your reply.
    you mean to say i have to create a separate NIOSll project n import my previous design.?
    can i do the vice-versa,like aft creating a separate NIOSll project n import NIOSll processor as IP on current *.bdf file?



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  4. #4
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    Re: How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 na

    Yes, you should be able to do it in either way. I've done it the way I mentioned because it seemed easier, but cannot remember exactly why I chose that way...


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  5. #5
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    Re: How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 na

    Thanks for your reply.
    I will try in above mentioned way and if it doesn't work then i will try in ur way.
    I am trying to interface a LCD and a keypad with the NIOSll. For that how should i go with the design of NIOSll. what all things i may require like, clock,I/O,uart.
    As i know i need to define things which i need while designing. Please let me know the modules which i need to include while design so that my LCD and KEYPAD can be interfaced.

    i am getting an error while compiling C code written for NIOSll saying "Template is required"- Do u have any idea about dis error.?



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  6. #6
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    Re: How to link a FPGA design and a NIOSll processor as a sigle FPGA design in DE0 na

    You can start from an example NIOS II project. You will see what kind of modules are needed. Also, when you add your cores as IP to NIOS project, you can add the core to Avalon bus. It is useful if your core has memory type interface.
    Sorry, I have no idea about that error...



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