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Xilinx ISE with SystemVerilog

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siddharthakala

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A few days back I got a warning on Xilinx ISE after synthesizing a design which said something like - Certain features are only available in SystemVerilog mode. Since then I have been trying to see how to activate this "SystemVerilog mode" but didnt get a clue about it. Does anyone know if there is any such feature that allows you to use SystemVerilog for writing synthesizable code in Xilinx ISE?

I am using Xilinx ISE 13.2.

Is there any other synthesis tools that support SystemVerilog for synthesis. I have Synplify but it doesnt support SV as well.
 

Care to post the code fragment that resulted in that error? XST doesn't support SV as far as I know. If it did, xilinx would surely be bragging about it in the release notes. :p

And I was under the impression that recent versions of Synplify did support SV synthesis...
 
According to my Xilinx FAE, the very latest version of XST does support some SV constructs, though I have not verified this myself. Synplify does support SystemVerilog and has done so for several years. That's what we use since XST has not supported SV in the past.

r.b.
 

I would be interested to know what those "some SV constructs" are. Last time I checked it didn't even do something trivial like "always_ff".

Just did a sanity check. Nope, XST 13.4 still doesn't do always_ff. It looks all pretty and syntax highlighted in the ISE editor, but that's about it.
 

I did forget to mention that it is for Virtex 7 FPGAs and above. And it may only be for the new toolsuite.

r.b.
 
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rberek could you mention the command line switches that need to be turned on to support system verilog constructs such as always_ff

and

which ISE version supports always_ff?
 

I just checked and the new toolsuite which supports SV is not generally available yet. I have never used it so I'm afraid I won't be much help there!
 

rberek Dude !

if you happen to ask this question to the AE, please let us know the response.

Thanks
 

mrflibble said:
Care to post the code fragment that resulted in that error? XST doesn't support SV as far as I know. If it did, xilinx would surely be bragging about it in the release notes. :p

And I was under the impression that recent versions of Synplify did support SV synthesis...
Click to expand...

I actually changed the code to remove all the warnings and didnt care about the SV warning at that time, and its been quite some time so I dont remember what it was.

The Synplify tool that I have is specific for Lattice FPGAs only, maybe thats why I dont have SV support. Also, I have just used it a few times, maybe I am mistaking, but, I didnt see any SV file option in the Add/Create new file options.
 

@tariq786
rberek Dude !

if you happen to ask this question to the AE, please let us know the response.
Click to expand...

The tool will be quite different than ISE is today, so I'm sure we will all have to learn how to set it up. I have it available to me but I don't have any time to check it out


@guitarguy12387

No XST support. Support is planned for 14.1
Click to expand...

Further to your comment, the release is planned for mid-year, but Webpacks probably won't see it until later.

r.b.
 
rberek said:
The tool will be quite different than ISE is today, so I'm sure we will all have to learn how to set it up. I have it available to me but I don't have any time to check it out.
Click to expand...

Oh the irony! I don't have it available to me but do have the time to check it out. :p

Further to your comment, the release is planned for mid-year, but Webpacks probably won't see it until later.
Click to expand...

It's been in ISE N+1 for a while now, so waiting a bit longer won't make a lot of difference. But good to know that it at least exists in tangible form out there doing the beta rounds with select customers. :)
 

Quartus II (Altera) is supporting SystemVerilog (in a limited but quite useful extent).
 
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