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VHDL - comparing memory arrays

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shaiko

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Hello,

I'd like to compare two memory arrays in real time (the elements of the array are changing) and output a true or false flag accordingly. Will the following code work:

process (memory_array_1, memory_array_2, flag) is
begin
for i in 0 to memory_depth - 1 loop
if memory_array_1(i) = memory_array_2(i) then
flag <= '1';
else
flag <= '1';
end if;
end loop;
end process;
 

Assumed the involved memory arrays are FPGA block RAM, it will not work. You should review the memory block specification to understand why. (There must be a clock and you can only access one memory location per clock cycle).

In addition, the flag is meaningless in the present code. Apparently, you're lacking an exact definition of flag meaning.
 

so, the following also want work?

if (memory_array_1(0) = memory_array_2(0)) and (memory_array_1(1) = memory_array_2(1)) then
flag <= '1';
else
flag <= '0';
end if;

Also, what do you mean by: "the flag is meaningless"?
I need some variable to evaluate if the comparasion is true or false...
 
Last edited:

The flag problem is trivial. I guess you would want to set the flag to matched before the loop and reset it in case of any mismatch. The more serious problem is about prerequisites of block memory usage, if it's inteded at all.
 

FvM,

I've seen working designs that implement a memory array and at the same time concatenate all the memory cells to one long vector. for example:

---------------------------------------------------------
type memory is array (0 to 2) of unsigned(7 downto 0);
signal fifo: memory;
signal concatenated_fifo_cells: unsigned(23 downto 0);

begin

concatenated_fifo_cells <= fifo(0) & fifo(1) & fifo(2); -- write to the fifo is implemented under a synchronous process
---------------------------------------------------------


"you can only access one memory location per clock cycle"
If what you're saying is correct, how is the code above possible? (all 3 cells of the memory block are combinatorially concatenated to a single vector)
 

If what you're saying is correct, how is the code above possible?
Click to expand...
It's not possible with block RAM. I guess, you should review the "working examples" more thoroughly. In any case, it's important to understand the basic properties of synchronous RAM.

A real working example could involve a block RAM of larger cell size, e.g. 24 bit. It can be accessed in byte entities as well. But it hardly won't be inferred from a description like you gave above.

You can review e.g. the Altera Quartus software manual paragraph about Mixed-Width Dual-Port RAM.
 

I understand what you're saying.
But your basic assumption is that block RAM is used.

I never said that. "memory_array" may be implemented using FF's.
If FF's are used, will the following work?

process (memory_array_1, memory_array_2, flag) is
begin
for i in 0 to memory_depth - 1 loop
if memory_array_1(i) = memory_array_2(i) then
flag <= '1';
else
flag <= '1';
end if;
end loop;
end process;
 

I think, my post has been referring to block RAM very clearly. Your code can work with FF arrays, if you change the flag assignment to something reasonable. You're still copying the meaningless code from post #2.

Code: 
flag <= '1';
for i in 0 to memory_depth - 1 loop
  if memory_array_1(i) /= memory_array_2(i) then
    flag <= '0';
  end if;
end loop;
 

sorry, I didn't notice that I assign '1' in both cases.
I meant to write it like this:
-----------------------------------------------------------
process (memory_array_1, memory_array_2, flag) is
begin
for i in 0 to memory_depth - 1 loop
if memory_array_1(i) = memory_array_2(i) then
flag <= '1';
else
flag <= '0';
end if;
end loop;
end process;
-----------------------------------------------------------


With every change in memory_array_1 or memory_array_2 the process will be accessed and the condition will be evaluated.

---------- Post added at 18:59 ---------- Previous post was at 17:55 ----------

What do you think of the above?
 

The flag handling is still erroneous. Now flag is only reflecting the last compare.
With every change in memory_array_1 or memory_array_2 the process will be accessed and the condition will be evaluated.
Click to expand...
Sensitivity lists are ignored in synthesis.
 

FvM,

What do you think about this code?

-----------------------------------------
process (data_1, data_2, result) is
begin
if data_1 = data_2 then
result <= '1';
else
result <= '0';
end if;
end process;
-----------------------------------------

Assuming that data_1 and data_2 are vectors - the above shall synthesize to a simple combinatorial comparator.
Other than the "loop" statetment, it's no different from what I wrote before...so why do you say that the flag handling is erroneous?
 

It's correct for a single compare, but not for an array compare as in post #9. Here the compare result for array elements 0 to memory_depth-2 is lost respectively ignored. I still assume, that you want to check for match of all array elements, as shown in of post #8.
 

I think I understand what you're saying...With every loop iteration - "flag" gets overwritten so at the end it shows only the reslut of the last compare (vector index "memory_depth - 1").
Thanks for the persistance!
 

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