Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Reflectarray pattern optimization/phase-only synthesis to decrease the side lobe

Status
Not open for further replies.

panou

Member level 1
Joined
Jun 6, 2011
Messages
36
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Location
California
Activity points
1,510
Hello all,

Anyone has experiences on this topic: reflectarray pattern optimization or phase-only synthesis? It is aim to decrease the SLL. I checked some papers, and some people are using Intersection approach, or GA algorithm.

I am wondering what's the procedure to do phase-only synthesis on reflectarray? I think I have to write own code to calculate the pattern of reflectarray first. Then what should I do?

Thanks.
Panou
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top