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hold check on half cycle paths

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pradeeppiskala

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How is the hold violation checked for half cycle paths?
Is it same as that of full cycle path? hold slack = insertion delay - hold time of the register (neglecting skew)
 

yes . This is same as normal hold checking but we consider half of the time period.


Thanks,
Narendra chava.
 

Normally for half cycle paths hold would be met easily. But as the clock period is shrinking now u might see hold violations also for half cycle paths.

The hold analysis would be same and as u know hold is not dependent on the clock period.
 

pradeeppiskala said:
https://obrazki.elektroda.pl/10_1320307338.jpg

which edge will be considered for hold slack calculation ( positive edge or negative edge)?


Since we are launching the data and capturing in the same cycle, how is hold defined. will hold not depend half clock period in half cycle path?
Click to expand...

As indicated in the diagram. The capture flop is a negative triggered flop.
Just think the edges of the capture where the data gets latched.
So here the hold check for capture shown in the figure is for the second pulse of the launch clock and not first one.

Hope its clear now.
 
pradeeppiskala said:
https://obrazki.elektroda.pl/10_1320307338.jpg

which edge will be considered for hold slack calculation ( positive edge or negative edge)?


Since we are launching the data and capturing in the same cycle, how is hold defined. will hold not depend half clock period in half cycle path?
Click to expand...

Hold check means, we've to verify that is the launched data is capturing at same edge( launched edge), and if the launched data is capturing at same edge then previously launched data will be corrupted, so we check for hold at launching edge and if it is violated then we have to try to fix that violation to prevent from capturing at same edge...so for half cycle paths also, hold check will be done at launch edge...hope it is clear for you..
 

sharif.shiek said:
Hold check means, we've to verify that is the launched data is capturing at same edge( launched edge), and if the launched data is capturing at same edge then previously launched data will be corrupted, so we check for hold at launching edge and if it is violated then we have to try to fix that violation to prevent from capturing at same edge...so for half cycle paths also, hold check will be done at launch edge...hope it is clear for you..
Click to expand...

Hold is time for which the input data has to be stable after the clock transition. since reg1 is launching the data at positive edge and reg2 is capturing at negative edge, only reg2 can go into hold violation. so , shouldn't we consider the negative edge(capture edge) for hold check?

In this case we are capturing the data in the same cycle, but the data at the both the flops is not latched at the same time.
 
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pradeeppiskala said:
Hold is time for which the input data has to be stable after the clock transition. since reg1 is launching the data at positive edge and reg2 is capturing at negative edge, reg2 can go into hold violation. so , shouldn't we consider the negative edge(capture edge) for hold check?

In this case we are capturing the data in the same cycle, but the data at the both the flops is not latched at the same time.
Click to expand...

No, that's what i'm saying...hold check ensures that data shouldn't be launched immediately, it should hold for sometime at launching edge, then only previously launched data will be captured at capture edge efficiently...refer some hold docs..you may get clarity

Hold time is also a timing parameter associated with Flip Flops and all other sequential devices. The Hold time is used to further satisfy the minimum pulse width requirement for the first (Master) latch that makes up a flip flop. The input must not change until enough time has passed after the clock tick to guarantee the master latch is fully disabled. More simply, hold time is the amount of time that an input signal (to a sequential device) must be stable (unchanging) after the clock tick in order to guarantee minimum pulse width and thus avoid possible metastability.

in above..minimum time is nothing but hold time which should be lessthen than the comb delay between flops...hope u can understand
 
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Hi Sharif,

Hold time should be less than the combi delay between the flops...Its not the other way round!!

@pradeep..

Hold check is done one edge prior to the capture edge.
Now if ur clock A has 10ns time period so its edges are 0 10 20 30 40
clock B also at 10ns but fall edge its sensitive edges are 5 15 25 35

So for data being launched at 10ns will have
setup check at 15ns
hold check at 5ns

For muti-cycle paths, the hold analysis can be done at one edge prior to capture edge or will moved to the edge corresponding to the launch edge...depending on the design flow.

cheers,
 
phoenixpavan said:
Hi Sharif,

Hold time should be less than the combi delay between the flops...Its not the other way round!!

@pradeep..

Hold check is done one edge prior to the capture edge.
Now if ur clock A has 10ns time period so its edges are 0 10 20 30 40
clock B also at 10ns but fall edge its sensitive edges are 5 15 25 35

So for data being launched at 10ns will have
setup check at 15ns
hold check at 5ns

For muti-cycle paths, the hold analysis can be done at one edge prior to capture edge or will moved to the edge corresponding to the launch edge...depending on the design flow.

cheers,
Click to expand...

thanks. got it.

but will hold depend on clock period in half cycle paths since the registers latch data at different time?

hold is independent of clock in full cycle paths since the registers latch data at the same instant. confused about hold in half cycle path since they latch at different times.
 

Since no one answered this last question, I will even if a few months late. YES, in a half cycle path your hold check will be affected by your period.

Here is how I like to think of it.

In the case of rising to falling on the same clock, data leaves flop1 at time 0 and must reach flop2 by the next falling edge which is half the clock period. This is the setup check.
Now, you need to make sure that the data doesn't change before it is flopped. This is the hold check.

You can think of this as checking hold at one edge prior as suggest by phoenixpavan, but hold also checks the next edge of the launching clock against the same capture edge. If the clocks are the same, both of these methods are the same and most STA tools will move the edges to the earliest alignment anyway.

Using his example, data launched at 10ns will be captured by the neg edge flop at 15ns. The next launch edge is at 20ns, so you need to check that the data launched at 20ns arrives after the original capture edge of 15ns. An STA tool will use the earliest alignment, which would be 10ns and 5ns just as he determined.

However, when you start using mixed frequencies it is apparent the two methods are not equivalent, and you must use the worst case.

For instance if your clock a is 2x your neg edge clock b.

So clock a has pos edges at 0 5 10 15 20 25 ...
and clock b has neg edges at 5 15 25 35 ...

The setup check by default uses one cycle of the capture clock, so capture will be at 15ns, and the worst case launch edge would be at 10ns giving you a 5ns period. This will be moved to the earliest alignment which is launch at 0ns capture at 5ns.
Now the hold check will be the next launch edge against the same capture edge, or 5ns and 5ns. This will not be reduced to 0 and 0 because 0 is not a valid capture time for the negative edge clock.

If you used phoenixpavan's methodology, you would still launch at 0ns, but now check hold one cycle earlier on the capture clock which would be -5ns. Moved to the first positive time alignment you would get launch at 10ns capture at 5ns, which is incorrect and allow massive hold violations to be missed.
 
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Thanks for the detailed explanation.

clock A is 2x(frequency) clock B: Yes, then hold check will be at 15ns launch and 15ns capture, 5ns launch and 5ns capture.
 

jdwk said:
Since no one answered this last question, I will even if a few months late. YES, in a half cycle path your hold check will be affected by your period.

Here is how I like to think of it.

In the case of rising to falling on the same clock, data leaves flop1 at time 0 and must reach flop2 by the next falling edge which is half the clock period. This is the setup check.
Now, you need to make sure that the data doesn't change before it is flopped. This is the hold check.

You can think of this as checking hold at one edge prior as suggest by phoenixpavan, but hold also checks the next edge of the launching clock against the same capture edge. If the clocks are the same, both of these methods are the same and most STA tools will move the edges to the earliest alignment anyway.

Using his example, data launched at 10ns will be captured by the neg edge flop at 15ns. The next launch edge is at 20ns, so you need to check that the data launched at 20ns arrives after the original capture edge of 15ns. An STA tool will use the earliest alignment, which would be 10ns and 5ns just as he determined.

However, when you start using mixed frequencies it is apparent the two methods are not equivalent, and you must use the worst case.

For instance if your clock a is 2x your neg edge clock b.

So clock a has pos edges at 0 5 10 15 20 25 ...
and clock b has neg edges at 5 15 25 35 ...

The setup check by default uses one cycle of the capture clock, so capture will be at 15ns, and the worst case launch edge would be at 10ns giving you a 5ns period. This will be moved to the earliest alignment which is launch at 0ns capture at 5ns.
Now the hold check will be the next launch edge against the same capture edge, or 5ns and 5ns. This will not be reduced to 0 and 0 because 0 is not a valid capture time for the negative edge clock.

If you used phoenixpavan's methodology, you would still launch at 0ns, but now check hold one cycle earlier on the capture clock which would be -5ns. Moved to the first positive time alignment you would get launch at 10ns capture at 5ns, which is incorrect and allow massive hold violations to be missed.
Click to expand...


Hi,

I am still not clear with all these explanations.

I have a few basic questions.

1) Assume both launch and capture clocks are in the same clock domain

Case1: Launch flop is rise edge triggered and capture flop is fall edge triggered
Assume clock period =5 ns
For setup: Launch is at 0 ns and capture is at 2.5 ns
For hold: The hold check is always done one cycle ahead of capture edge setup.In this case it would be 2.5-5=-2.5.which would not be possible.So the hold check is done with the next edge of setup which is at 5ns.So hold check happens between 2.5 ns and 5.0 ns.So in the timing report what would be the clock edge at the capture edge.

Case2: Launch flop is fall triggered and capture flop is rise triggered
Assume clock period =5 ns
For setup: launch at 2.5 ns , capture is done at 5 ns
For hold: launch at 2.5 ns , capture happens at 0ns

If can get some clarity on this, I guess I can figure out the other 2 cases in which launch and capture clocks are of different frequencies.
 

sg123,

This is how I think about it.

In normal full cycle paths, hold is checked on same edge. Since it is on the same edge, hold is independent of clock period.

But in half cycle path, hold is checked at the present launch and previous capture.
1) clock period = 5ns
Launch: 0 5 10 15
capture: 2.5 7.5

As you have mentioned, hold will checked for launch at 5ns and capture at 2.5ns. Since 2.5ns is difference, half clock period, hold is dependent on clock period in half cycle paths.

Let me know if I am not clear.
 

sg123 said:
Hi,

I am still not clear with all these explanations.

I have a few basic questions.

1) Assume both launch and capture clocks are in the same clock domain

Case1: Launch flop is rise edge triggered and capture flop is fall edge triggered
Assume clock period =5 ns
For setup: Launch is at 0 ns and capture is at 2.5 ns
For hold: The hold check is always done one cycle ahead of capture edge setup.In this case it would be 2.5-5=-2.5.which would not be possible.So the hold check is done with the next edge of setup which is at 5ns.So hold check happens between 2.5 ns and 5.0 ns.So in the timing report what would be the clock edge at the capture edge.

Case2: Launch flop is fall triggered and capture flop is rise triggered
Assume clock period =5 ns
For setup: launch at 2.5 ns , capture is done at 5 ns
For hold: launch at 2.5 ns , capture happens at 0ns

If can get some clarity on this, I guess I can figure out the other 2 cases in which launch and capture clocks are of different frequencies.
Click to expand...

Pradeep is correct. Case 1 hold, launch 5ns, capture 2.5ns. Case 2 hold, launch 2.5ns, capture 0ns.

Half cycle paths help hold. It gives you half the time to meet setup timing, but then you don't have to worry about clock skew anymore. This is useful for slow clocks or source synchronous clocks where setup is not a concern but skew is.
 

Can someone give the hold equation for half cycle path ? I have been asked this twice in interviews.

And I believe for setup, below equation is correct. If not then please correct me.

Tclk/2 >= Tc-q + Tcomb + Tsetup

I worked out on the hold equation for half cycle path. Is this correct ?

Tclk/2 + Tc-q + Tcomb >= Thold
 
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KaptainBug said:
Can someone give the hold equation for half cycle path ? I have been asked this twice in interviews.

And I believe for setup, below equation is correct. If not then please correct me.

Tclk/2 >= Tc-q + Tcomb + Tsetup

I worked out on the hold equation for half cycle path. Is this correct ?

Tclk/2 + Tc-q + Tcomb >= Thold
Click to expand...

A hold requirement is the amount of time the data must arrive after the clock on a given flop. This is a characterization done for each type of flop for a given PVT (process, voltage and temperature). Often times this number is negative to help your hold margin.

In a half cycle path your launch and capture flops are of opposite edge trigger type. Don't really think of it as half the period though, as some clocks do not have 50/50 duty cycles, but for simplicity we'll assume they are.

Your clock to q delay is just part of your launch path, the launch path actually starts from the clock source, and includes the entire clock path delay, the ck->o delay of the flop, and the rest of the delay from the output to the input of the receiver.

The capture path is the entire delay from the clock source to the clock pin of the capturing flop. The difference between clock delay to the driver and to the receiver is called skew, and if there was no difference the world would never see a hold violation.

Your setup equation is correct except you are missing the vital capture delay.

setup margin = Clock period/2 - launch path - setup requirement + capture path

for hold, the launch and capture are just reversed.

hold margin = Clock period/2 + launch path - hold requirement - capture path

This is one of those things that you just have to go over, draw out a bunch and one day it will just click and then you'll wonder how it ever didn't make sense. Unfortunately, it's not really easy to explain with a forum post. You really need to look at some timing reports. Maybe someone has some non-confidential ones they could post.

When I interview people I never ask for someone just to regurgitate formulas, I am interested if they know how that formula came to be.
 
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Thank you for the detailed explanation.

jdwk said:
A hold requirement is the amount of time the data must arrive before the clock on a given flop.
Click to expand...

Did you mean the amount of time the data must be stable 'after' the clock ?

jdwk said:
Your setup equation is correct except you are missing the vital capture delay.

setup margin = Clock period/2 - launch path - setup requirement + capture path

for hold, the launch and capture are just reversed.

hold margin = Clock period/2 + launch path - hold requirement - capture path
Click to expand...

I understand that,
launch path = Tc-q + Tcomb
but what is capture path component in the equation ? Is this the skew ? If yes, then here is the final equation. Let me know if they are correct.

Tclk/2 + Tskew >= Tc-q + Tcomb + Tsetup
Tclk/2 + Tc-q + Tcomb >= Thold + Tskew
 

Yep sorry about that, after. Need to proofread a little better.

Skew = delay from clock source to clock pin of launch flop - delay from clock source to clock pin of capture flop

Positive skew helps setup and hurts hold.

Your equations look correct. You'll notice a half cycle hold violation almost never happens. I've dealt with it only once in silicon and it was because we deliberately skewed the two clocks to help hold in the other direction, and we accidentally false pathed the half cycle path.
 

Appreciate your response. Thank you.
 
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