VHDL code to add elements of an array, together, in one clock cycle?

I'm implementing a series of multiply-and-accumulate functions in a filter window. All the multiplies happen in a single clock cycle (coded with a FOR loop and results stored into an array). Those products are then summed in groups of 4 and stored into another array, and so forth, until I have a single array of partial sums...

I have these results of intermediate summations being stored in a 1-dimensional array of std_logic_vector. In my last processing stage I want to sum the values in each element of that array, together, and store the result in a single register. In C it would be something like:

mac_result = 0;
for(j = 0; j < num_elements; j++){
mac_result = mac_result + partial_sums[j];
}

I tried doing basically that in VHDL using a variable, then assigning the variable to a signal, but I ended up getting a lot of X's in simulation. The issue is that the number of partial sums (and therefore the number of array elements) will change depending upon the size of the 2D window filter, and so I can't code this using a fixed number of additions. Anyway, what would you do?

usually, you only do a single aditition per clock cycle. trying to add 3 or more numbers is going to hit your timing performace. Any reason you cant pipeline it?

TrickyDicky said:

usually, you only do a single aditition per clock cycle. trying to add 3 or more numbers is going to hit your timing performace. Any reason you cant pipeline it?

Click to expand...

Actually the design is (overall) pipelined. I begin with M x N multiplication operations (nominally 7x7). This produces 49 products in a single clock (at the expense of area) stored in a 1D array of std_logic_vector. I use a FOR loop to sum 4 products together at a time (12 additions producing 12 fisrt-stage partial sums, in 12-element array) on the next clock. I use another FOR loop to sum 4 of the first-stage sums together at a time (3 additions producing 3 second-stage partial sums, in a 3-element array) on the next clock. Now I have 3 second-stage partial sums in a 3-element array, together with one "extra product" (the 49th) that has been delayed to match the pipeline depth. I need to sum three array elements together...plus the extra product...as my last stage of addition.

I can create the code to sum groups of 4 registers together, and store the results into a *separate* array of registers. I cannot figure out how to create the code to sum elements *within* the same array when the number of elements within that array is variable. In a 7x7 case it will contain 3 second-stage sums...in a 9x9 case it will contain 5, etc.

The array size shouldnt vary over time. The array size should be fixed at compile time. SO you would use generics to set the size, and then you can work out how many pipeline stages are required.