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What is the effect of black box module on the overall test coverage while doing ATPG?

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Pinto$

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Hi,
My design is having a black box module. if i am doing ATPG generation, test coverage is just coming out to be 70%. for that is black box is responsible? What should I do for increasing the test coverage?
I am new to DFT. Please reply.
Regards,
Pinto$
 

if the ATPG tool does not know the functionnality of a black box, it assume his output "drive" X, so all logic behing will have a reduce coverage. If you know the state in scan of the black box, you could define this value in the model or via atpg commands.
In general, atpg tool could report which fault is not cover and the reason (uncontrolable...).
 
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---------- Post added at 22:39 ---------- Previous post was at 22:37 ----------
rca said:
if the ATPG tool does not know the functionnality of a black box, it assume his output "drive" X, so all logic behing will have a reduce coverage. If you know the state in scan of the black box, you could define this value in the model or via atpg commands.
In general, atpg tool could report which fault is not cover and the reason (uncontrolable...).
Click to expand...

What has to be done other than defining of the black boxed module? Does FastScan support defining values for the black box?
how to remove the ATPG untestable faults? Can it only be done by increasing the no. of patterns and sequential depth or are there other factors also?
 

1- you could write a model for your black box (fastscan model) or fastscan is able to read verilog "model". We used it for our analog views, with very simplest description. All outputs are define at the expected values when the design will be in scan.
2-you can not "remove" untestable fault. The tool anaylze the fault list and some are not accessible, some are "merge" with others.... To increase the coverage, you could add some test points, or loop-back around or inside the black box (if you could).
 
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rca said:
1- you could write a model for your black box (fastscan model) or fastscan is able to read verilog "model". We used it for our analog views, with very simplest description. All outputs are define at the expected values when the design will be in scan.
2-you can not "remove" untestable fault. The tool anaylze the fault list and some are not accessible, some are "merge" with others.... To increase the coverage, you could add some test points, or loop-back around or inside the black box (if you could).
Click to expand...

Hi rca,
I tried to fix the unknown outputs from the black box by inserting the test points i.e. control and observe points but then I am not able to generate test patterns. What problem could be there? Do I have to remove the test points before generating the test patterns and what will happen to the patterns generated by using test points?

Regards,
Pinto$
 

the test point is just added flop, that will be included in the scan chain, and should increase the coverage.
checks the test point is properly inserted and added in the scan chains.
 
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