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    Sensibility list / adc clock

    Hello all,
    I have a (probably stupid) question about a clock signal provided by a rotary encoder on a motor. I have to use this digital signal to sample an analog signal with an external ADC, this signal is in fact the clock of my ADC. My question is : can I create a process with the encoder output in the sensibility list ? or do I have to synchronize the process with the master clock of the FPGA and then test the edge of my external input ?

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    Re: Sensibility list / adc clock

    The question can't be answered without analyzing the respective data pathes. It's sometimes suitable or even necessary to create additional clock domains in a FPGA design, but you also should consider how you want to transfer the data consistently between clock domains. If the speed of the external signal allows synchronous processing within the main clock domain, it's clearly the preferred method.



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    Re: Sensibility list / adc clock

    The question can't be answered without analyzing the respective data pathes. It's sometimes suitable or even necessary to create additional clock domains in a FPGA design, but you also should consider how you want to transfer the data consistently between clock domains. If the speed of the external signal allows synchronous processing within the main clock domain, it's clearly the preferred method.


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    Re: Sensibility list / adc clock

    Hello,
    Thanks a lot for your reply. The encoder provide a 600kHz "clock" signal and the clock of the FPGA is 50MHz, so I think I can synchronize the ADC clock with the FPGA clock.



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    Re: Sensibility list / adc clock

    If its running that slow, I would just use the slow "clock" as a clock enable, and run all logic at 50MHz. Its quite easy to detect rising edges at that speed.



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