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  1. #1
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    Instantiation In a Loop in Verilog

    Hi,

    I want to instantiate a module 16 time and it is so boring.
    Is there a way that I can use a "for loop" and only one istantiation?
    I used these syntax and ModelSim doed not accept it.
    I should say that I need my code to be synthesizable also.

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  2. #2
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    Re: Instantiation In a Loop in Verilog

    Seems like you lacking a good Verilog text book or tutorial. Read about the generate loop statement.



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  3. #3
    Advanced Member level 3
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    Re: Instantiation In a Loop in Verilog

    you can use "generate" method to do so!



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